Synchronous memory device having automatic precharge

ABSTRACT

The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.  
     The present invention also includes a protocol for master and slave devices to communicate on the bus and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices. The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data and control information for memory addresses up to 40 bits wide.

FIELD OF THE INVENTION

[0001] An integrated circuit bus interface for computer and videosystems is described which allows high speed transfer of blocks of data,particularly to and from memory devices, with reduced power consumptionand increased system reliability. A new method of physicallyimplementing the bus architecture is also described.

BACKGROUND OF THE INVENTION

[0002] Semiconductor computer memories have traditionally been designedand structured to use one memory device for each bit, or small group ofbits, of any individual computer word, where the word size is governedby the choice of computer. Typical word sizes range from 4 to 64 bits.Each memory device typically is connected in parallel to a series ofaddress lines and connected to one of a series of data lines. When thecomputer seeks to read from or write to a specific memory location, anaddress is put on the address lines and some or all of the memorydevices are activated using a separate device select line for eachneeded device. One or more devices may be connected to each data linebut typically only a small number of data lines are connected to asingle memory device. Thus data line 0 is connected to device(s) 0, dataline 1 is connected to device(s) 1, and so on. Data is thus accessed orprovided in parallel for each memory read or write operation. For thesystem to operate properly, every single memory bit in every memorydevice must operate dependably and correctly.

[0003] To understand the concept of the present invention, it is helpfulto review the architecture of conventional memory devices. Internal tonearly all types of memory devices (including the most widely usedDynamic Random Access Memory (DRAM), Static RAM (SRAM) and Read OnlyMemory (ROM) devices), a large number of bits are accessed in paralleleach time the system carries out a memory access cycle. However, only asmall percentage of accessed bits which are available internally eachtime the memory device is cycled ever make it across the device boundaryto the external world.

[0004] Referring to FIG. 1, all modern DRAM, SRAM and ROM designs haveinternal architectures with row (word) lines 5 and column (bit) lines 6to allow the memory cells to tile a two dimensional area 1. One bit ofdata is stored at the intersection of each word and bit line. When aparticular word line is enabled, all of the corresponding data bits aretransferred onto the bit lines. Some prior art DRAMs take advantage ofthis organization to reduce the number of pins needed to transmit theaddress. The address of a given memory cell is split into two addresses,row and column, each of which can be multiplexed over a bus only half aswide as the memory cell address of the prior art would have required.

COMPARISON WITH PRIOR ART

[0005] Prior art memory systems have attempted to solve the problem ofhigh speed access to memory with limited success.

[0006] U.S. Pat. No. 3,821,715 (Hoff et. al.), was issued to IntelCorporation for the earliest 4-bit micro-processor. That patentdescribes a bus connecting a single central processing unit (CPU) withmultiple RAMs and ROMs. That bus multiplexes addresses and data over a4-bit wide bus and uses point-to-point control signals to selectparticular RAMs or ROMs. The access time is fixed and only a singleprocessing element is permitted. There is no block-mode type ofoperation, and most important, not all of the interface signals betweenthe devices are bused (the ROM and RAM control lines and the RAM selectlines are point-to-point).

[0007] In U.S. Pat. No. 4,315,308 (Jackson), a bus connecting a singleCPU-to a bus interface unit is described. The invention uses multiplexedaddress, data, and control information over a single 16-bit wide bus.Block-mode operations are defined, with the length of the block sent aspart of the control sequence. In addition, variable access-timeoperations using a “stretch” cycle signal are provided. There are nomultiple processing elements and no capability for multiple outstandingrequests, and again, not all of the interface signals are bused.

[0008] In U.S. Pat. No. 4,449,207 (Kung, et. al.), a DRAM is describedwhich multiplexes address and data on an internal bus. The externalinterface to this DRAM is conventional, with separate control, addressand data connections.

[0009] In U.S. Pat. Nos. 4,764,846 and 4,706,166 (Go), a 3-D packagearrangement of stacked die with connections along a single edge isdescribed. Such packages are difficult to use because of thepoint-to-point wiring required to interconnect conventional memorydevices with processing elements. Both patents describe complex schemesfor solving these problems. No attempt is made to solve the problem bychanging the interface.

[0010] In U.S. Pat. No. 3,969,706 (Proebsting, et. al.), the currentstate-of-the-art DRAM interface is described. The address is two-waymultiplexed, and there are separate pins for data and control (RAS, CAS,WE, CS). The number of pins grows with the size of the DRAM, and many ofthe connections must be made point-to-point in a memory system usingsuch DRAMs.

[0011] There are many backplane buses described in the prior art, butnot in the combination described or having the features of thisinvention. Many backplane buses multiplex addresses and data on a singlebus (e.g., the NU bus). ELXSI and others have implementedsplit-transaction buses (U.S. Pat. Nos. 4,595,923 and 4,481,625(Roberts)). ELXSI has also implemented a relatively low-voltage-swingcurrent-mode ECL driver (approximately 1 V swing). Address-spaceregisters are implemented on most backplane buses, as is some form ofblock mode operation.

[0012] Nearly all modern backplane buses implement some type ofarbitration scheme, but the arbitration scheme used in this inventiondiffers from each of these. U.S. Pat. No. 4,837,682 (Culler), U.S Pat.No. 4,818,985 (Ikeda), U.S. Pat. No. 4,779,089 (Theus) and U.S. Pat. No.4,745,548 (Blahut) describe prior art schemes. All involve either log Nextra signals, (Theus, Blahut), where N is the number of potential busrequesters, or additional delay to get control of the bus (Ikeda,Culler). None of the buses described in patents or other literature useonly bused connections. All contain some point-to-point connections onthe backplane. None of the other aspects of this invention such as powerreduction by fetching each data block from a single device or compactand low-cost 3-D packaging even apply to backplane buses.

[0013] The clocking scheme used in this invention has not been usedbefore and in fact would be difficult to implement in backplane busesdue to the signal degradation caused by connector stubs. U.S. Pat. No.4,247,817 (Heller) describes a clocking scheme using two clock lines,but relies on ramp-shaped clock signals in contrast to the normalrise-time signals used in the present invention.

[0014] In U.S. Pat. No. 4,646,279 (Voss), a video RAM is described whichimplements a parallel-load, serial-out shift register on the output of aDRAM. This generally allows greatly improved bandwidth (and has beenextended to 2, 4 and greater width shift-out paths.) The rest of theinterfaces to the DRAM (RAS, CAS, multiplexed address, etc.) remain thesame as for conventional DRAMS.

[0015] One object of the present invention is to use a new bus interfacebuilt into semiconductor devices to support high-speed access to largeblocks of data from a single memory device by an external user of thedata, such as a microprocessor, in an efficient and cost-effectivemanner.

[0016] Another object of this invention is to provide a clocking schemeto permit high speed clock signals to be sent along the bus with minimalclock skew between devices.

[0017] Another object of this invention is to allow mapping outdefective memory devices or portions of memory devices.

[0018] Another object of this invention is to provide a method fordistinguishing otherwise identical devices by assigning a uniqueidentifier to each device.

[0019] Yet another object of this invention is to provide a method fortransferring address, data and control information over a relativelynarrow bus and to provide a method of bus arbitration when multipledevices seek to use the bus simultaneously.

[0020] Another object of this invention is to provide a method ofdistributing a high-speed memory cache within the DRAM chips of a memorysystem which is much more effective than previous cache methods.

[0021] Another object of this invention is to provide devices,especially DRAMs, suitable for use with the bus architecture of theinvention.

SUMMARY OF INVENTION

[0022] The present invention includes a memory subsystem comprising atleast two semiconductor devices, including at least one memory device,connected in parallel to a bus, where the bus includes a plurality ofbus lines for carrying substantially all address, data and controlinformation needed by said memory devices, where the control informationincludes device-select information and the bus has substantially fewerbus lines than the number of bits in a single address, and the buscarries device-select information without the need for separatedevice-select lines connected directly to individual devices.

[0023] Referring to FIG. 2, a standard DRAM 13, 14, ROM (or SRAM) 12,microprocessor CPU 11, I/O device, disk controller or other specialpurpose device such as a high speed switch is modified to use a whollybus-based interface rather than the prior art combination ofpoint-to-point and bus-based wiring used with conventional versions ofthese devices. The new bus includes clock signals, power and multiplexedaddress, data and control signals. In a preferred implementation, 8 busdata lines and an AddressValid bus line carry address, data and controlinformation for memory addresses up to 40 bits wide. Persons skilled inthe art will recognize that 16 bus data lines or other numbers of busdata lines can be used to implement the teaching of this invention. Thenew bus is used to connect elements such as memory, peripheral, switchand processing units.

[0024] In the system of this invention, DRAMs and other devices receiveaddress and control information over the bus and transmit or receiverequested data over the same bus. Each memory device contains only asingle bus interface with no other signal pins. Other devices that maybe included in the system can connect to the bus and other non-buslines, such as input/output lines. The bus supports large data blocktransfers and split transactions to allow a user to achieve high busutilization. This ability to rapidly read or write a large block of datato one single device at a time is an important advantage of thisinvention.

[0025] The DRAMs that connect to this bus differ from conventional DRAMsin a number of ways. Registers are provided which may store controlinformation, device identification, device-type and other informationappropriate for the chip such as the address range for each independentportion of the device. New bus interface circuits must be added and theinternals of prior art DRAM devices need to be modified so they canprovide and accept data to and from the bus at the peak data rate of thebus. This requires changes to the column access circuitry in the DRAM,with only a minimal increase in die size. A circuit is provided togenerate a low skew internal device clock for devices on the bus, andother circuits provide for demultiplexing input and multiplexing outputsignals.

[0026] High bus bandwidth is achieved by running the bus at a very highclock rate (hundreds of MHz). This high clock rate is made possible bythe constrained environment of the bus. The bus lines arecontrolled-impedance, doubly-terminated lines. For a data rate of 500MHz, the maximum bus propagation time is less than 1 ns (the physicalbus length is about 10 cm). In addition, because of the packaging used,the pitch of the pins can be very close to the pitch of the pads. Theloading on the bus resulting from the individual devices is very small.In a preferred implementation, this generally allows stub capacitancesof 1-2 pF and inductances of 0.5-2 nH. Each device 15, 16, 17, shown inFIG. 3, only has pins on one side and these pins connect directly to thebus 18. A transceiver device 19 can be included to interface multipleunits to a higher order bus through pins 20.

[0027] A primary result of the architecture of this invention is toincrease the bandwidth of DRAM access. The invention also reducesmanufacturing and production costs, power consumption, and increasespacking density and system reliability.

BRIEF DESCRIPTION OF THE DRAWINGS

[0028]FIG. 1 is a diagram which illustrates the basic 2-D organizationof memory devices.

[0029]FIG. 2 is a schematic block diagram which illustrates the parallelconnection of all bus lines and the serial Reset line to each device inthe system.

[0030]FIG. 3 is a perspective view of a system of the invention whichillustrates the 3-D packaging of semiconductor devices on the primarybus.

[0031]FIG. 4 shows the format of a request packet.

[0032]FIG. 5 shows the format of a retry response from a slave.

[0033]FIG. 6 shows the bus cycles after a request packet collisionoccurs on the bus and how arbitration is handled.

[0034]FIG. 7 shows the timing whereby signals from two devices canoverlap temporarily and drive the bus at the same time.

[0035]FIG. 8 shows the connection and timing between bus clocks anddevices on the bus.

[0036]FIG. 9 is a perspective view showing how transceivers can be usedto connect a number of bus units to a transceiver bus.

[0037]FIG. 10 is a block and schematic diagram of input/output circuitryused to connect devices to the bus.

[0038]FIG. 11 is a schematic diagram of a clocked sense-amplifier usedas a bus input receiver.

[0039]FIG. 12 is a block diagram showing how the internal device clockis generated from two bus clock signals using a set of adjustable delaylines.

[0040]FIG. 13 is a timing diagram showing the relationship of signals inthe block diagram of FIG. 12.

[0041]FIG. 14 is timing diagram of a preferred means of implementing thereset procedure of this invention.

[0042]FIG. 15 is a diagram illustrating the general organization of a 4Mbit DRAM divided into 8 subarrays.

DETAILED DESCRIPTION

[0043] The present invention is designed to provide a high speed,multiplexed bus for communication between processing devices and memorydevices and to provide devices adapted for use in the bus system. Theinvention can also be used to connect processing devices and otherdevices, such as I/O interfaces or disk controllers, with or withoutmemory devices on the bus. The bus consists of a relatively small numberof lines connected in parallel to each device on the bus. The buscarries substantially all address, data and control information neededby devices for communication with other devices on the bus. In manysystems using the present invention, the bus carries almost every signalbetween every device in the entire system. There is no need for separatedevice-select lines since device-select information for each device onthe bus is carried over the bus. There is no need for separate addressand data lines because address and data information can be sent over thesame lines. Using the organization described herein, very largeaddresses (40 bits in the preferred implementation) and large datablocks (1024 bytes) can be sent over a small number of bus lines (8 plusone control line in the preferred implementation).

[0044] Virtually all of the signals needed by a computer system can besent over-the bus. Persons skilled in the art recognize that certaindevices, such as CPUs, may be connected to other signal lines andpossibly to independent buses, for example a bus to an independent cachememory, in addition to the bus of this invention. Certain devices, forexample cross-point switches, could be connected to multiple,independent buses of this invention. In the preferred implementation,memory devices are provided that have no connections other than the busconnections described herein and CPUs are provided that use the bus ofthis invention as the principal, if not exclusive, connection to memoryand to other devices on the bus.

[0045] All modern DRAM, SRAM and ROM designs have internal architectureswith row (word) and column (bit) lines to efficiently tile a 2-D area.Referring to FIG. 1, one bit of data is stored at the intersection ofeach word line 5 and bit line 6. When a particular word line is enabled,all of the corresponding data bits are transferred onto the bit lines.This data, about 4000 bits at a time in a 4 MBit DRAM, is then loadedinto column sense amplifiers 3 and held for use by the I/O circuits.

[0046] In the invention presented here, the data from the senseamplifiers is enabled 32 bits at a time onto an internal device busrunning at approximately 125 MHz. This internal device bus moves thedata to the periphery of the devices where the data is multiplexed intoan 8-bit wide external bus interface, running at approximately 500 MHz.

[0047] The bus architecture of this invention connects master or buscontroller devices, such as CPUs, Direct Memory Access devices (DMAS) orFloating Point Units (FPUs), and slave devices, such as DRAM, SRAM orROM memory devices. A slave device responds to control signals; a mastersends control signals. Persons skilled in the art realize that somedevices may behave as both master and slave at various times, dependingon the mode of operation and the state of the system. For example, amemory device will typically have only slave functions, while a DMAcontroller, disk controller or CPU may include both slave and masterfunctions. Many other semiconductor devices, including I/O devices, diskcontrollers, or other special purpose devices such as high speedswitches can be modified for use with the bus of this invention.

[0048] Each semiconductor device contains a set of internal registers,preferably including a device identification (device ID) register, adevice-type descriptor register, control registers and other registerscontaining other information relevant to that type of device. In apreferred implementation, semiconductor devices connected to the buscontain registers which specify the memory addresses contained withinthat device and access-time registers which store a set of one or moredelay times at which the device can or should be available to send orreceive data.

[0049] Most of these registers can be modified and preferably are set aspart of an initialization sequence that occurs when the system ispowered up or reset. During the initialization sequence each device onthe bus is assigned a unique device ID number, which is stored in thedevice ID register. A bus master can then use these device ID numbers toaccess and set appropriate registers in other devices, includingaccess-time registers, control registers, and memory registers, toconfigure the system. Each slave may have one or several access-timeregisters (four in a preferred embodiment). In a preferred embodiment,one access-time register in each slave is permanently orsemi-permanently programmed with a fixed value to facilitate certaincontrol functions. A preferred implementation of an initializationsequence is described below in more detail.

[0050] All information sent between master devices and slave devices issent over the external bus, which, for example, may be 8 bits wide. Thisis accomplished by defining a protocol whereby a master device, such asa microprocessor, seizes exclusive control of the external bus (i.e.,becomes the bus master) and initiates a bus transaction by sending arequest packet (a sequence of bytes comprising address and controlinformation) to one or more slave devices on the bus. An address canconsist of 16 to 40 or more bits according to the teachings of thisinvention. Each slave on the bus must decode the request packet to seeif that slave needs to respond to the packet. The slave that the packetis directed to must then begin any internal processes needed to carryout the requested bus transaction at the requested time. The requestingmaster may also need to transact certain internal processes before thebus transaction begins. After a specified access time the slave(s)respond by returning one or more bytes (8 bits) of data or by storinginformation made available from the bus. More than one access time canbe provided to allow different types of responses to occur at differenttimes.

[0051] A request packet and the corresponding bus access are separatedby a selected number of bus cycles, allowing the bus to be used in theintervening bus cycles by the same or other masters for additionalrequests or brief bus accesses. Thus multiple, independent accesses arepermitted, allowing maximum utilization of the bus for transfer of shortblocks of data. Transfers of long blocks of data use the bus efficientlyeven without overlap because the overhead due to bus address, controland access times is small compared to the total time to request andtransfer the block.

[0052] Device Address Mapping

[0053] Another unique aspect of this invention is that each memorydevice is a complete, independent memory subsystem with all thefunctionality of a prior art memory board in a conventionalbackplane-bus computer system. Individual memory devices may contain asingle memory section or may be subdivided into more than one discretememory section. Memory devices preferably include memory addressregisters for each discrete memory section. A failed memory device (oreven a subsection of a device) can be “mapped out” with only the loss ofa small fraction of the memory, maintaining essentially full systemcapability. Mapping out bad devices can be accomplished in two ways,both compatible with this invention.

[0054] The preferred method uses address registers in each memory device(or independent discrete portion thereof) to store information whichdefines the range of bus addresses to which this memory device willrespond. This is similar to prior art schemes used in memory boards inconventional backplane bus systems. The address registers can include asingle pointer, usually pointing to a block of known size, a pointer anda fixed or variable block size value or two pointers, one pointing tothe beginning and one to the end (or to the “top” and “bottom”) of eachmemory block. By appropriate settings of the address registers, a seriesof functional memory devices or discrete memory sections can be made torespond to a contiguous range of addresses, giving the system access toa contiguous block of good memory, limited primarily by the number ofgood devices connected to the bus. A block of memory in a first memorydevice or memory section can be assigned a certain range of addresses,then a block of memory in a next memory device or memory section can beassigned addresses starting with an address one higher (or lower,depending on the memory structure) than the last address of the previousblock.

[0055] Preferred devices for use in this invention include device-typeregister information specifying the type of chip, including how muchmemory is available in what configuration on that device. A master canperform an appropriate memory test, such as reading and writing eachmemory cell in one or more selected orders, to test proper functioningof each accessible discrete portion of memory (based in part oninformation like device ID number and device-type) and write addressvalues (up to 40 bits in the preferred embodiment, 10¹² bytes),preferably contiguous, into device address-space registers.Non-functional or impaired memory sections can be assigned a specialaddress value which the system can interpret to avoid using that memory.

[0056] The second approach puts the burden of avoiding the bad deviceson the system master or masters. CPUs and DMA controllers typically havesome sort of translation look-aside buffers (TLBs) which map virtual tophysical (bus) addresses. With relatively simple software, the TLBs canbe programmed to use only working memory (data structures describingfunctional memories are easily generated). For masters which don'tcontain TLBs (for example, a video display generator), a small, simpleRAM can be used to map a contiguous range of addresses onto theaddresses of the functional memory devices.

[0057] Either scheme works and permits a system to have a significantpercentage of non-functional devices and still continue to operate withthe memory which remains. This means that systems built with thisinvention will have much improved reliability over existing systems,including the ability to build systems with almost no field failures.

[0058] Bus

[0059] The preferred bus architecture of this invention comprises 11signals: BusData[0:7]; AddrValid; Clk1 and Clk2; plus an input referencelevel and power and ground lines connected in parallel to each device.Signals are driven onto the bus during conventional bus cycles. Thenotation “Signal[i:j]” refers to a specific range of signals or lines,for example, BusData[0:7] means BusData0, BusDatal, . . . , BusData7.The bus lines for BusData[0:7] signals form a byte-wide, multiplexeddata/address/control bus. AddrValid is used to indicate when the bus isholding a valid address request, and instructs a slave to decode the busdata as an address and, if the address is included on that slave, tohandle the pending request. The two clocks together provide asynchronized, high speed clock for all the devices on the bus. Inaddition to the bused signals, there is one other line (ResetIn,ResetOut) connecting each device in series for use during initializationto assign every device in the system a unique device ID number(described below in detail).

[0060] To facilitate the extremely high data rate of this external busrelative to the gate delays of the internal logic, the bus cycles aregrouped into pairs of even/odd cycles. Note that all devices connectedto a bus should preferably use the same even/odd labeling of bus cyclesand preferably should begin operations on even cycles. This is enforcedby the clocking scheme.

[0061] Protocol and Bus Operation

[0062] The bus uses a relatively simple, synchronous, split-transaction,block-oriented protocol for bus transactions. One of the goals of thesystem is to keep the intelligence concentrated in the masters, thuskeeping the slaves as simple as possible (since there are typically manymore slaves than masters). To reduce the complexity of the slaves, aslave should preferably respond to a request in a specified time,sufficient to allow the slave to begin or possibly complete adevice-internal phase including any internal actions that must precedethe subsequent bus access phase. The time for this bus access phase isknown to all devices on the bus—each master being responsible for makingsure that the bus will be free when the bus access begins. Thus theslaves never worry about arbitrating for the bus. This approacheliminates arbitration in single master systems, and also makes theslave-bus interface simpler.

[0063] In a preferred implementation of the invention, to initiate a bustransfer over the bus, a master sends out a request packet, a contiguousseries of bytes containing address and control information. It ispreferable to use a request packet containing an even number of bytesand also preferable to start each packet on an even bus cycle.

[0064] The device-select function is handled using the bus data lines.AddrValid is driven, which instructs all slaves to decode the requestpacket address, determine whether they contain the requested address,and if they do, provide the data back to the master (in the case of aread request) or accept data from the master (in the case of a writerequest) in a data block transfer. A master can also select a specificdevice by transmitting a device ID number in a request packet. In apreferred implementation, a special device ID number is chosen toindicate that the packet should be interpreted by all devices on thebus. This allows a master to broadcast a message, for example to set aselected control register of all devices with the same value.

[0065] The data block transfer occurs later at a time specified in therequest packet control information, preferably beginning on an evencycle. A device begins a data block transfer almost immediately with adevice-internal phase as the device initiates certain functions, such assetting up memory addressing, before the bus access phase begins. Thetime after which a data block is driven onto the bus lines is selectedfrom values stored in slave access-time registers. The timing of datafor reads and writes is preferably the same; the only difference iswhich device drives the bus. For reads, the slave drives the bus and themaster latches the values from the bus. For writes the master drives thebus and the selected slave latches the values from the bus.

[0066] In a preferred implementation of this invention shown in FIG. 4,a request packet 22 contains 6 bytes of data 4.5 address bytes and 1.5control bytes. Each request packet uses all nine bits of the multiplexeddata/address lines (AddrValid 23+BusData[0:7] 24) for all six bytes ofthe request packet. Setting 23 AddrValid=1 in an otherwise unused evencycle indicates the start of an request packet (control information). Ina valid request packet, AddrValid 27 must be 0 in the last byte.Asserting this signal in the last byte invalidates the request packet.This is used for the collision detection and arbitration logic(described below). Bytes 25-26 contain the first 35 address bits,Address[0:35]. The last byte contains AddrValid 27 (the invalidationswitch) and 28, the remaining address bits, Address[36:39], andBlockSize[0:3] (control information).

[0067] The first byte contains two 4 bit fields containing controlinformation, AccessType[0:3], an op code (operation code) which, forexample, specifies the type of access, and Master[0:3], a positionreserved for the master sending the packet to include its master IDnumber. Only master numbers 1 through 15 are allowed—master number 0 isreserved for special system commands. Any packet with Master[0:3]=0 isan invalid or special packet and is treated accordingly.

[0068] The AccessType field specifies whether the requested operation isa read or write and the type of access, for example, whether it is tothe control registers or other parts of the device, such as memory. In apreferred implementation, AccessType[0] is a Read/Write switch: if it isa 1, then the operation calls for a read from the slave (the slave toread the requested memory block and drive the memory contents onto thebus); if it is a 0, the operation calls for a write into the slave (theslave to read data from the bus and write it to memory). AccessType[1:3]provides up to 8 different access types for a slave. AccessType[1:2]preferably indicates the timing of the response, which is stored in anaccess-time register, AccessRegN. The choice of access-time register canbe selected directly by having a certain op code select that register,or indirectly by having a slave respond to selected op codes withpre-selected access times (see table below). The remaining bit,AccessType[3] may be used to send additional information about therequest to the slaves.

[0069] One special type of access is control register access, whichinvolves addressing a selected register in a selected Slave. In thepreferred implementation of this invention, AccessType[1:3] equal tozero indicates a control register request and the address field of thepacket indicates the desired control register. For example, the mostsignificant two bytes can be the device ID number (specifying whichslave is being addressed) and the least significant three bytes canspecify a register address and may also represent or include data to beloaded into that control register. Control register accesses are used toinitialize the access-time registers, so it is preferable to use a fixedresponse time which can be preprogrammed or even hard wired, for examplethe value in AccessReg0, preferably 8 cycles. Control register accesscan also be used to initialize or modify other registers, includingaddress registers.

[0070] The method of this invention provides for access mode controlspecifically for the DRAMs. One such access mode determines whether theaccess is page mode or normal RAS access. In normal mode (inconventional DRAMS and in this invention), the DRAM column sense amps orlatches have been precharged to a value intermediate between logical 0and 1. This precharging allows access to a row in the RAM to begin assoon as the access request for either inputs (writes) or outputs (reads)is received and allows the column sense amps to sense data quickly. Inpage mode (both conventional and in this invention), the DRAM holds thedata in the column sense amps or latches from the previous read or writeoperation. If a subsequent request to access data is directed to thesame row, the DRAM does not need to wait for the data to be sensed (ithas been sensed already) and access time for this data is much shorterthan the normal access time. Page mode generally allows much fasteraccess to data but to a smaller block of data (equal to the number ofsense amps). However, if the requested data is not in the selected row,the access time is longer than the normal access time, since the requestmust wait for the RAM to precharge before the normal mode access canstart. Two access-time registers in each DRAM preferably contain theaccess times to be used for normal and for page-mode accesses,respectively.

[0071] The access mode also determines whether the DRAM should prechargethe sense amplifiers or should save the contents of the sense amps for asubsequent page mode access. Typical settings are “precharge afternormal access” and “save after page mode access” but “precharge afterpage mode access” or “save after normal access” are allowed, selectablemodes of operation. The DRAM can also be set to precharge the sense ampsif they are not accessed for a selected period of time.

[0072] In page mode, the data stored in the DRAM sense amplifiers may beaccessed within much less time than it takes to read out data in normalmode (˜10-20 nS vs. 40-100 nS). This data may be kept available for longperiods. However, if these sense amps (and hence bit lines) are notprecharged after an access, a subsequent access to a different memoryword (row) will suffer a precharge time penalty of about 40-100 nSbecause the sense amps must precharge before latching in a new value.

[0073] The contents of the sense amps thus may be held and used as acache, allowing faster, repetitive access to small blocks of data.DRAM-based page-mode caches have been attempted in the prior art usingconventional DRAM organizations but they are not very effective becauseseveral chips are required per computer word. Such a conventionalpage-mode cache contains many bits (for example, 32 chips×4 Kbits) buthas very few independent storage entries. In other words, at any givenpoint in time the sense amps hold only a few different blocks or memory“locales” (a single block of 4K words, in the example above).Simulations have shown that upwards of 100 blocks are required toachieve high hit rates (>9.0% of requests find the requested dataalready in cache memory) regardless of the size of each block. See, forexample, Anant Agarwal, et. al., “An Analytic Cache Model,” ACMTransactions on Computer Systems, Vol. 7(2), pp. 184-215 (May 1989).

[0074] The organization of memory in the present invention allows eachDRAM to hold one or more (4 for 4 MBit DRAMS) separately-addressed andindependent blocks of data. A personal computer or workstation with 100such DRAMs (i.e. 400 blocks or locales) can achieve extremely high, veryrepeatable hit rates (98-99% on average) as compared to the lower(50-80%), widely varying hit rates using DRAMS organized in theconventional fashion. Further, because of the time penalty associatedwith the deferred precharge on a “miss” of the page-mode cache, theconventional DRAM-based page-mode cache generally has been found to workless well than no cache at all.

[0075] For DRAM slave access, the access types are preferably used inthe following way: AccessType[1:3] Use AccessTime 0 Control RegisterFixed, 8[AccessReg0] Access 1 Unused Fixed, 8[AccessReg0] 2-3 UnusedAccessReg1 4-5 Page Mode DRAM AccessReg2 access 6-7 Normal DRAM accessAccessReg3

[0076] Persons skilled in the art will recognize that a series ofavailable bits could be designated as switches for controlling theseaccess modes. For example:

[0077] AccessType[2]=page mode/normal switch

[0078] AccessTypef[3]=precharge/save-data switch

[0079] BlockSize[0:3] specifies the size of the data block transfer. IfBlockSize[0] is 0, the remaining bits are the binary representation ofthe block size (0-7). If BlockSize[0] is 1, then the remaining bits givethe block size as a binary power of 2, from 8 to 1024. A zero-lengthblock can be interpreted as a special command, for example, to refresh aDRAM without returning any data, or to change the DRAM from page mode tonormal access mode or vice-versa. BlockSize[0:2] Number of Bytes inBlock 0-7 0-7 respectively  8 8  9 16 10 32 11 64 12 128 13 256 14 51215 1024

[0080] Persons skilled in the art will recognize that other block sizeencoding schemes or values can be used.

[0081] In most cases, a slave will respond at the selected access timeby reading or writing data from or to the bus over bus linesBusData:[0:7] and AddrValid will be at logical 0. In a preferredembodiment, substantially each memory access will involve only a singlememory device, that is, a single block will be read from or written to asingle memory device.

[0082] Retry Format

[0083] In some cases, a slave may not be able to respond correctly to arequest, e.g., for a read or write. In such a situation, the slaveshould return an error message, sometimes called a N(o)ACK(nowledge) orretry message. The retry message can include information about thecondition requiring a retry, but this increases system requirements forcircuitry in both slave and masters. A simple message indicating onlythat an error has occured allows for a less complex slave, and themaster can take whatever action is needed to understand and correct thecause of the error.

[0084] For example, under certain conditions a slave might not be ableto supply the requested data. During a page-mode access, the DRAMselected must be in page mode and the requested address must match theaddress of the data held in the sense amps or latches. Each DRAM cancheck for this match during a page-mode access. If no match is found,the DRAM begins precharging and returns a retry message to the masterduring the first cycle of the data block (the rest of the returned blockis ignored). The master then must wait for the precharge time (which isset to accommodate the type of slave in question, stored in a specialregister, PreChargeReg), and then resend the request as a normal DRAMaccess (AccessType=6 or 7).

[0085] In the preferred form of the present invention, a slave signals aretry by driving Addrvalid true at the time the slave was supposed tobegin reading or writing data. A master which expected to write to thatslave must monitor AddrValid during the write and take corrective actionif it detects a retry message. FIG. 5 illustrates the format of a retrymessage 28 which is useful for read requests, consisting of 23AddrValid=1 with Master[0:3]=0 in the first (even) cycle. Note thatAddrValid is normally 0 for data block transfers and that there is nomaster 0 (only 1 through 15 are allowed). All DRAMs and masters caneasily recognize such a packet as an invalid request packet, andtherefore a retry message. In this type of bus transaction all of thefields except for Master[0:3] and AddrValid 23 may be used asinformation fields, although in the implementation described, thecontents are undefined. Persons skilled in the art recognize thatanother method of signifying a retry message is to add a DataInvalidline and signal to the bus. This signal could be asserted in the case ofa NACK.

[0086] Bus Arbitration

[0087] In the case of a single master, there are by definition noarbitration problems. The master sends request packets and keeps trackof periods when the bus will be busy in response to that packet. Themaster can schedule multiple requests so that the corresponding datablock transfers do not overlap.

[0088] The bus architecture of this invention is also useful inconfigurations with multiple masters. When two or more masters are onthe same bus, each master must keep track of all the pendingtransactions, so each master knows when it can send a request packet andaccess the corresponding data block transfer. Situations will arise,however, where two or more masters send a request packet at about thesame time and the multiple requests must be detected, then sorted out bysome sort of bus arbitration.

[0089] There are many ways for each master to keep track of when the busis and will be busy. A simple method is for each master to maintain abus-busy data structure, for example by maintaining two pointers, one toindicate the earliest point in the future when the bus will be busy andthe other to indicate the earliest point in the future when the bus willbe free, that is, the end of the latest pending data block transfer.Using this information, each master can determine whether and when thereis enough time to send a request packet (as described above underProtocol) before the bus becomes busy with another data block transferand whether the corresponding data block transfer will interfere withpending bus transactions. Thus each master must read every requestpacket and update its bus-busy data structure to maintain informationabout when the bus is and will be free.

[0090] With two or more masters on the bus, masters will occasionallytransmit independent request packets during the same bus cycle. Thosemultiple requests will collide as each such master drives the bussimultaneously with different information, resulting in scrambledrequest information and neither desired data block transfer. In apreferred form of the invention, each devise on the bus seeking to writea logical 1 on a BusData or AddrValid line drives that line with acurrent sufficient to sustain a voltage greater than or equal to thehigh-logic value for the system. Devices do not drive lines that shouldhave a logical 0; those lines are simply held at a voltage correspondingto a low-logic value. Each master tests the voltage on at least some,preferably all, bus data and the AddrValid lines so the master candetect a logical ‘1’ where the expected level is ‘0’ on a line that itdoes not drive during a given bus cycle but another master does drive.

[0091] Another way to detect collisions is to select one or more buslines for collision signalling. Each master sending a request drivesthat line or lines and monitors the selected lines for more than thenormal drive current (or a logical value of “>1”), indicating requestsby more than one master. Persons skilled in the art will recognize thatthis can be implemented with a protocol involving BusData and AddrValidlines or could be implemented using an additional bus line.

[0092] In the preferred form of this invention, each master detectscollisions by monitoring lines which it does not drive to see if anothermaster is driving those lines. Referring to FIG. 4, the first byte ofthe request packet includes the number of each master attempting to usethe bus (Master[0:3]). If two masters send packet requests starting atthe same point in time, the master numbers will be logical “or”edtogether by at least those masters, and thus one or both of the masters,by monitoring the data on the bus and comparing what it sent, can detecta collision. For instance if requests by masters number 2 (0010) and 5(0101) collide, the bus will be driven with the value Master[0:3]=7(0010+0101=0111). Master number 5 will detect that the signalMaster[23]=1 and master 2 will detect that Master[1] and Master[3]=1,telling both masters that a collision has occurred. Another example ismasters 2 and 11, for which the bus will be driven with the valueMaster[0:3]=11 (0010+1011=1011), and although master 11 can't readilydetect this collision, master 2 can. When any collision is detected,each master detecting a collision drives the value of AddrValid 27 inbyte 5 of the request packet 22 to 1, which is detected by all masters,including master 11 in the second example above, and forces a busarbitration cycle, described below.

[0093] Another collision condition may arise where master A sends arequest packet in cycle 0 and master B tries to send a request packetstarting in cycle 2 of the first request packet, thereby overlapping thefirst request packet. This will occur from time to time because the busoperates at high speeds, thus the logic in a second-initiating mastermay not be fast enough to detect a request initiated by a first masterin cycle 0 and to react fast enough by delaying its own request. MasterB eventually notices that it wasn't supposed to try to send a requestpacket (and consequently almost surely destroyed the address that masterA was trying to send), and, as in the example above of a simultaneouscollision, drives a 1 on AddrValid during byte 5 of the first requestpacket 27 forcing an arbitration. The logic in the preferredimplementation is fast enough that a master should detect a requestpacket by another master by cycle 3 of the first request packet, so nomaster is likely to attempt to send a potentially colliding requestpacket later than cycle 2.

[0094] Slave devices not need to detect a collision directly, but theymust wait to do anything irrecoverable until the last byte (byte 5) isread to ensure that the packet is valid. A request packet withMaster[0:3] equal to 0 (a retry signal) is ignored and does not cause acollision. The subsequent bytes of such a packet are ignored.

[0095] To begin arbitration after a collision, the masters wait apreselected number of cycles after the aborted request packet (4 cyclesin a preferred implementation), then use the next free cycle toarbitrate for the bus (the next available even cycle in the preferredimplementation). Each colliding master signals to all other collidingmasters that it seeks to send a request packet, a priority is assignedto each of the colliding masters, then each master is allowed to makeits request in the order of that priority.

[0096]FIG. 6 illustrates one preferred way of implementing thisarbitration. Each colliding master signals its intent to send a requestpacket by driving a single BusData line during a single bus cyclecorresponding to its assigned master number (1 -15 in the presentexample). During two-byte arbitration cycle 29, byte 0 is allocated torequests 1-7 from masters 1-7, respectively, (bit 0 is not used) andbyte 1 is allocated to requests 8-15 from masters 8-15, respectively. Atleast one device and preferably each colliding master reads the valueson the bus during the arbitration cycles to determine and store whichmasters desire to use the bus. Persons skilled in the art will recognizethat a single byte can be allocated for arbitration requests if thesystem includes more bus lines than masters. More than 15 masters can beaccommodated by using additional bus cycles.

[0097] A fixed priority scheme (preferably using the master numbers,selecting lowest numbers first) is then used to prioritize, thensequence the requests in a bus arbitration queue which is maintained byat least one device. These requests are queued by each master in thebus-busy data structure and no further requests are allowed until thebus arbitration queue is cleared. Persons skilled in the art willrecognize that other priority schemes can be used, including assigningpriority according to the physical location of each master.

[0098] System Configuration/Reset

[0099] In the bus-based system of this invention, a mechanism isprovided to give each device on the bus a unique device identifier(device ID) after power-up or under other conditions as desired orneeded by the system. A master can then use this device ID to access aspecific device, particularly to set or modify registers of thespecified device, including the control and address registers. In thepreferred embodiment, one master is assigned to carry out the entiresystem configuration process. The master provides a series of uniquedevice ID numbers for each unique device connected to the bus system. Inthe preferred embodiment, each device connected to the bus contains aspecial device-type register which specifies the type of device, forinstance CPU, 4 MBit memory, 64 MBit memory or disk controller. Theconfiguration master should check each device, determine the device typeand set appropriate control registers, including access-time registers.The configuration master should check each memory device and set allappropriate memory address registers.

[0100] One means to set up unique device ID numbers is to have eachdevice to select a device ID in sequence and store the value in aninternal device ID register. For example, a master can pass sequentialdevice ID numbers through shift registers in each of a series ofdevices, or pass a token from device to device whereby the device withthe token reads in device ID information from another line or lines. Ina preferred embodiment, device ID numbers are assigned to devicesaccording to their physical relationship, for instance, their orderalong the bus.

[0101] In a preferred embodiment of this invention, the device IDsetting is accomplished using a pair of pins on each device, ResetIn andResetOut. These pins handle normal logic signals and are used onlyduring device ID configuration. On each rising edge of the clock, eachdevice copies ResetIn (an input) into a four-stage reset shift register.The output of the reset shift register is connected to ResetOut, whichin turn connects to ResetIn for the next sequentially connected device.Substantially all devices on the bus are thereby daisy-chained together.A first reset signal, for example, while ResetIn at a device is alogical 1, or when a selected bit of the reset shift register goes fromzero to non-zero, causes the device to hard reset, for example byclearing all internal registers and resetting all state machines. Asecond reset signal, for example, the falling edge of ResetIn combinedwith changeable values on the external bus, causes that device to latchthe contents of the external bus into the internal device ID register(Device[0:7]).

[0102] To reset all devices on a bus, a master sets the ResetIn line ofthe first device to a “1” for long enough to ensure that all devices onthe bus have been reset (4 cycles times the number of devices—note thatthe maximum number of devices on the preferred bus configuration is 256(8 bits), so that 1024 cycles is always enough time to reset alldevices.) Then ResetIn is dropped to “0” and the BusData lines aredriven with the first followed by successive device ID numbers, changingafter every 4 clock pulses. Successive devices set those device IDnumbers into the corresponding device ID register as the falling edge ofResetln propagates through the shift registers of the daisy-chaineddevices. FIG. 14 shows ResetIn at a first device going low while amaster drives a first device ID onto the bus data lines BusData[0:3].The first device then latches in that first device ID. After four clockcycles, the master changes BusData[0:3] to the next device ID number andResetOut at the first device goes low, which pulls ResetIn for the nextdaisy-chained device low, allowing the next device to latch in the nextdevice ID number from BusData[0:3]. In the preferred embodiment, onemaster is assigned device ID 0 and it is the responsibility of thatmaster to control the ResetIn line and to drive successive device IDnumbers onto the bus at the appropriate times. In the preferredembodiment, each device waits two clock cycles after ResetIn goes lowbefore latching in a device ID number from BusData[0:3].

[0103] Persons skilled in the art recognize that longer device IDnumbers could be distributed to devices by having each device read inmultiple bytes from the bus and latch the values into the device IDregister. Persons skilled in the art also recognize that there arealternative ways of getting device ID numbers to unique devices. Forinstance, a series of sequential numbers could be clocked along theResetIn line and at a certain time each device could be instructed tolatch the current reset shift register value into the device IDregister.

[0104] The configuration master should choose and set an access time ineach access-time register in each slave to a period sufficiently long toallow the slave to perform an actual, desired memory access. Forexample, for a normal DRAM access, this time must be longer than the rowaddress strobe (RAS) access time. If this condition is not met, theslave may not deliver the correct data. The value stored in a slaveaccess-time register is preferably one-half the number of bus cycles forwhich the slave device should wait before using the bus in response to arequest. Thus an access time value of ‘1’ would indicate that the slaveshould not access the bus until at least two cycles after the last byteof the request packet has been received. The value of AccessRegO ispreferably fixed at 8 (cycles) to facilitate access to controlregisters.

[0105] The bus architecture of this invention can include more than onemaster device. The reset or initialization sequence should also includea determination of whether there are multiple masters on the bus, and ifso to assign unique master ID numbers to each. Persons skilled in theart will recognize that there are many ways of doing this. For instance,the master could poll each device to determine what type of device itis, for example, by reading a special register then, for each masterdevice, write the next available master ID number into a specialregister.

[0106] ECC

[0107] Error detection and correction (“ECC”) methods well known in theart can be implemented in this system. ECC information typically iscalculated for a block of data at the time that block of data is firstwritten into memory. The data block usually has an integral binary size,e.g. 256 bits, and the ECC information uses significantly fewer bits. Apotential problem arises in that each binary data block in prior artschemes typically is stored with the ECC bits appended, resulting in ablock size that is not an integral binary power.

[0108] In a preferred embodiment of this invention, ECC information isstored separately from the corresponding data, which can then be storedin blocks having integral binary size. ECC information and correspondingdata can be stored, for example, in separate DRAM devices. Data can beread without ECC using a single request packet, but to write or readerror-corrected data requires two request packets, one for the data anda second for the corresponding ECC information. ECC information may notalways be stored permanently and in some situations the ECC informationmay be available without sending a request packet or without a bus datablock transfer.

[0109] In a preferred embodiment, a standard data block size can beselected for use with ECC, and the ECC method will determine therequired number of bits of information in a corresponding ECC block.RAMs containing ECC information can be programmed to store an accesstime that is equal to: (1) the access time of the normal RAM (containingdata) plus the time to access a standard data block (for corrected data)minus the time to send a request packet (6 bytes); or (2) the accesstime of a normal RAM minus the time to access a standard ECC block minusthe time to send a request packet. To read a data block and thecorresponding ECC block, the master simply issues a request for the dataimmediately followed by a request for the ECC block. The ECC RAM willwait for the selected access time then drive its data onto the bus rightafter (in case (1) above)) the data RAM has finished driving out thedata block. Persons skilled in the art will recognize that the accesstime described in case (2) above can be used to drive ECC data beforethe data is driven onto the bus lines and will recognize that writingdata can be done by analogy with the method described for a read.Persons skilled in the art will also recognize the adjustments that mustbe made in the bus-busy structure and the request packet arbitrationmethods of this invention in order to accommodate these paired ECCrequests.

[0110] Since this system is quite flexible, the system designer canchoose the size of the data blocks and the number of ECC bits using thememory devices of this invention. Note that the data stream on the buscan be interpreted in various ways. For instance the sequence can be2^(n) data bytes followed by 2^(m) ECC bytes (or vice versa), or thesequence can be 2^(k) iterations of 8 data bytes plus 1 ECC byte. Otherinformation, such as information used by a directory-based cachecoherence scheme, can also be managed this way. See, for example, AnantAgarwal, et al., “Scaleable Directory Schemes for Cache Consistency,”15th International Symposium on Computer Architecture, June 1988, pp.280-289. Those skilled in the art will recognize alternative methods ofimplementing ECC schemes that are within the teachings of thisinvention.

[0111] Low Power 3-D Packaging

[0112] Another major advantage of this invention is that it drasticallyreduces the memory system power consumption. Nearly all the powerconsumed by a prior art DRAM is dissipated in performing row access. Byusing a single row access in a single RAM to supply all the bits for ablock request (compared to a row-access in each of multiple RAMs inconventional memory systems) the power per bit can be made very small.Since the power dissipated by memory devices using this invention issignificantly reduced, the devices potentially can be placed much closertogether than with conventional designs.

[0113] The bus architecture of this invention makes possible aninnovative 3-D packaging technology. By using a narrow, multiplexed(time-shared) bus, the pin count for an arbitrarily large memory devicecan be kept quite small—on the order of 20 pins. Moreover, this pincount can be kept constant from one generation of DRAM density to thenext. The low power dissipation allows each package to be smaller, withnarrower pin pitches (spacing between the IC pins). With current surfacemount technology supporting pin pitches as low as 20 mils, alloff-device connections can be implemented on a single edge of the memorydevice; Semiconductor die useful in this invention preferably haveconnections or pads along one edge of the die which can then be wired orotherwise connected to the package pins with wires having similarlengths. This geometry also allows for very short leads, preferably withan effective lead length of less than 4 mm. Furthermore, this inventionuses only bused interconnections, i.e., each pad on each device isconnected by the bus to the corresponding pad of each other device.

[0114] The use of a low pin count and an edge-connected bus permits asimple 3-D package, whereby the devices are stacked and the bus isconnected along a single edge of the stack. The fact that all of thesignals are bused is important for the implementation of a simple 3-Dstructure. Without this, the complexity of the “backplane” would be toodifficult to make cost effectively with current technology. Theindividual devices in a stack of the present invention can be packedquite tightly because of the low power dissipated by the entire memorysystem, permitting the devices to be stacked bumper-to-bumper or top tobottom. Conventional plastic-injection molded small outline (SO)packages can be used with a pitch of about 2.5 mm (100 mils), but theultimate limit would be the device die thickness, which is about anorder of magnitude smaller, 0.2-0.5 mm using current wafer technology.

[0115] Bus Electrical Description

[0116] By using devices with very low power dissipation and closephysical packing, the bus can be made quite short, which in turn allowsfor short propagation times and high data rates. The bus of a preferredembodiment of the present invention consists of a set ofresistor-terminated controlled impedance transmission lines which canoperate up to a data rate of 500 MHz (2 ns cycles). The characteristicsof the transmission lines are strongly affected by the loading caused bythe DRAMs (or other slaves) mounted on the bus. These devices add lumpedcapacitance to the lines which both lowers the impedance of the linesand decreases the transmission speed. In the loaded environment, the busimpedance is likely to be on the order of 25 ohms and the propagationvelocity about c/4 (c=the speed of light) or 7.5 cm/ns. To operate at a2 ns data rate, the transit time on the bus should preferably be keptunder 1 ns, to leave 1 ns for the setup and hold time of the inputreceivers (described below) plus clock skew. Thus the bus lines must bekept quite short, under about 8 cm for maximum performance. Lowerperformance systems may have much longer lines, e.g. a 4 ns bus may have24 cm lines (3 ns transit time, 1 ns setup and hold time).

[0117] In the preferred embodiment, the bus uses current source drivers.Each output must be able to sink 50 mA, which provides an output swingof about 500 mV or more. In the preferred embodiment of this invention,the bus is active low. The unasserted state (the high value) ispreferably considered a logical zero, and the asserted value (low state)is therefore a logical 1. Those skilled in the art understand that themethod of this invention can also be implemented using the oppositelogical relation to voltage. The value of the unasserted state is set bythe voltage on the termination resistors, and should be high enough toallow the outputs to act as current sources, while being as low aspossible to reduce power dissipation. These constraints may yield atermination voltage about 2V above ground in the preferredimplementation. Current source drivers cause the output voltage to beproportional to the sum of the sources driving the bus.

[0118] Referring to FIG. 7, although there is no stable condition wheretwo devices drive the bus at the same time, conditions can arise becauseof propagation delay on the wires where one device, A 41, can startdriving its part of the bus 44 while the bus is still being driven byanother device, B 42 (already asserting a logical 1 on the bus). In asystem using current drivers, when B 42 is driving the bus (before time46), the value at points 44 and 45 is logical 1. If B 42 switches off attime 46 just when A 41 switches on, the additional drive by device A 41causes the voltage at the output 44 of A 41 to drop briefly below thenormal value. The voltage returns to its normal value at time 47 whenthe effect of device B 42 turning off is felt. The voltage at point 45goes to logical 0 when device B 42 turns off, then drops at time 47 whenthe effect of device A 41 turning on is felt. Since the logical 1 drivenby current from device A 41 is propagated irrespective of the previousvalue on the bus, the value on the bus is guaranteed to settle after onetime of flight (t_(f)) delay, that is, the time it takes a signal topropagate from one end of the bus to the other. If a voltage drive wasused (as in ECL wired-ORing), a logical 1 on the bus (from device B 42being previously driven) would prevent the transition put out by deviceA 41 being felt at the most remote part of the system, e.g., device 43,until the turnoff waveform from device B 42 reached device A 41 plus onetime of flight delay, giving a worst case settling time of twice thetime of flight delay.

[0119] Clocking

[0120] Clocking a high speed bus accurately without introducing errordue to propagation delays can be implemented by having each devicemonitor two bus clock signals and then derive internally a device clock,the true system clock. The bus clock information can be sent on one ortwo lines to provide a mechanism for each bused device to generate aninternal device clock with zero skew relative to all the other deviceclocks. Referring to FIG. 8, in the preferred implementation, a busclock generator 50 at one end of the bus propagates an early bus clocksignal in one direction along the bus, for example on line 53 from leftto right, to the far end of the bus. The same clock signal then ispassed through the direct connection shown to a second line 54, andreturns as a late bus clock signal along the bus from the far end to theorigin, propagating from right to left. A single bus clock line can beused if it is left unterminated at the far end of the bus, allowing theearly bus clock signal to reflect back along the same line as a late busclock signal.

[0121]FIG. 8b illustrates how each device 51, 52 receives each of thetwo bus clock signals at a different time (because of propagation delayalong the wires), with constant midpoint in time between the two busclocks along the bus. At each device 51, 52, the rising edge 55 ofClock1 53 is followed by,the rising edge 56 of Clock2 54. Similarly, thefalling edge 57 of Clock1 53 is followed by the falling edge 58 ofClock2 54. This waveform relationship is observed at all other devicesalong the bus. Devices which are closer to the clock generator have agreater separation between Clock1 and Clock2 relative to devices fartherfrom the generator because of the longer time required for each clockpulse to traverse the bus and return along line 54, but the midpoint intime 59, 60 between corresponding rising or falling edges is fixedbecause, for any given device, the length of each clock line between thefar end of the bus and that device is equal. Each device must sample thetwo bus clocks and generate its own internal device clock at themidpoint of the two.

[0122] Clock distribution problems can be further reduced by using a busclock and device clock rate equal to the bus cycle data rate divided bytwo, that is, the bus clock period is twice the bus cycle period. Thus a500 MHz bus preferably uses a 250 MHz clock rate. This reduction infrequency provides two benefits. First it makes all signals on the bushave the same worst case data rates—data on a 500 MHz bus can onlychange every 2 ns. Second, clocking at half the bus cycle data ratemakes the labeling of the odd and even bus cycles trivial, for example,by defining even cycles to be those when the internal device clock is 0and odd cycles when the internal device clock is 1.

[0123] Multiple Buses

[0124] The limitation on bus length described above restricts the totalnumber of devices that can be placed on a single bus. Using 2.5 mmspacing between devices, a single 8 cm bus will hold about 32 devices.Persons skilled in the art will recognize certain applications of thepresent invention wherein the overall data rate on the bus is adequatebut memory or processing requirements necessitate a much larger numberof devices (many more than 32). Larger systems can easily be built usingthe teachings of this invention by using one or more memory subsystems,designated primary bus units, each of which consists of two or moredevices, typically 32 or close to the maximum allowed by bus designrequirements, connected to a transceiver device.

[0125] Referring to FIG. 9, each primary bus unit can be mounted on asingle circuit board 66, sometimes called a memory stick. Eachtransceiver device 19 in turn connects to a transceiver bus 65, similaror identical in electrical and other respects to the primary bus 18described at length above. In a preferred implementation, all mastersare situated on the transceiver bus so there are no transceiver delaysbetween masters and all memory devices are on primary bus units so thatall memory accesses experience an equivalent transceiver delay, butpersons skilled in the art will recognize how to implement systems whichhave masters on more than one bus unit and memory devices on thetransceiver bus as well as on primary bus units. In general, eachteaching of this invention which refers to a memory device can bepracticed using a transceiver device and one or more memory devices onan attached primay bus unit. Other devices, generically referred to asperipheral devices, including disk controllers, video controllers or I/Odevices can also be attached to either the transceiver bus or a primarybus unit, as desired. Persons skilled in the art will recognize how touse a single primary bus unit or multiple primary bus units as neededwith a transceiver bus in certain system designs.

[0126] The transceivers are quite simple in function. They detectrequest packets on the transceiver bus and transmit them to theirprimary bus unit. If the request packet calls for a write to a device ona transceiver's primary bus unit, that transceiver keeps track of theaccess time and block size and forwards all data from the transceiverbus to the primary bus unit during that time. The transceivers alsowatch their primary bus unit, forwarding any data that occurs there tothe transceiver bus. The high speed of the buses means that thetransceivers will need to be pipelined, and will require an additionalone or two cycle delay for data to pass through the transceiver ineither direction. Access times stored in masters on the transceiver busmust be increased to account for transceiver delay but access timesstored in slaves on a primary bus unit should not be modified.

[0127] Persons skilled in the art will recognize that a moresophisticated transceiver can control transmissions to and from primarybus units. An additional control line, TrncvrRW can be bused to alldevices on the transceiver bus, using that line in conjunction with theAddrValid line to indicate to all devices on the transceiver bus thatthe information on the data lines is: 1) a request packet, 2) valid datato a slave, 3) valid data from a slave, or 4) invalid data (or idlebus). Using this extra control line obviates the need for thetransceivers to keep track of when data needs to be forwarded from itsprimary bus to the transceiver bus—all transceivers send all data fromtheir primary bus to the transceiver bus whenever the control signalindicates condition 2) above. In a preferred implementation of thisinvention, if AddrValid and TrncvrRW are both low, there is no busactivity and the transceivers should remain in an idle state. Acontroller sending a request packet will drive AddrValid high,indicating to all devices on the transceiver bus that a request packetis being sent which each transceiver should forward to its primary busunit. Each controller seeking to write to a slave should drive bothAddrValid and TrncvrRW high, indicating valid data for a slave ispresent on the data lines. Each transceiver device will then transmitall data from the transceiver bus lines to each primary bus unit. Anycontroller expecting to receive information from a slave should alsodrive the TrncvrRW line high, but not drive AddrValid, therebyindicating to each transceiver to transmit any data coming from anyslave on its primary local bus to the transceiver bus. A still moresophisticated transceiver would recognize signals addressed to or comingfrom its primary bus unit and transmit signals only at requested times.

[0128] An example of the physical mounting of the transceivers is shownin FIG. 9. One important feature of this physical arrangement is tointegrate the bus of each transceiver 19 with the original bus of DRAMsor other devices 15, 16, 17 on the primary bus unit 66. The transceivers19 have pins on two sides, and are preferably mounted flat on theprimary bus unit with a first set of pins connected to primary bus 18. Asecond set of transceiver pins 20, preferably orthogonal to the firstset of pins, are oriented to allow the transceiver 19 to be attached tothe transceiver bus 65 in much the same way as the DRAMs were attachedto the primary bus unit. The transceiver bus can be generally planar andin a different plane, preferably orthogonal to the plane of each primarybus unit. The transceiver bus can also be generally circular withprimary bus units mounted perpendicular and tangential to thetransceiver bus.

[0129] Using this two level scheme allows one to easily build a systemthat contains over 500 slaves (16 buses of 32 DRAMs each). Personsskilled in the art can modify the device ID scheme described above toaccommodate more than 256 devices, for example by using a longer deviceID or by using additional registers to hold some of the device ID. Thisscheme can be extended in yet a third dimension to make a second-ordertransceiver bus, connecting multiple transceiver buses by aligningtransceiver bus units parallel to and on top of each other and busingcorresponding signal lines through a suitable transceiver. Using such asecond-order transceiver bus, one could connect many thousands of slavedevices into what is effectively a single bus.

[0130] Device Interface

[0131] The device interface to the high-speed bus can be divided intothree main parts. The first part is the electrical interface. This partincludes the input receivers, bus drivers and clock generationcircuitry. The second part contains the address comparison circuitry andtiming registers. This part takes the input request packet anddetermines if the request is for this device, and if it is, starts theinternal access and delivers the data to the pins at the correct time.The final part, specifically for memory devices such as DRAMs, is theDRAM column access path. This part needs to provide bandwidth into andout of the DRAM sense amps greater than the bandwidth provided byconventional DRAMs. The implementation of the electrical interface andDRAM column access path are described in more detail in the followingsections. Persons skilled in the art recognize how to modify prior-artaddress comparison circuitry and prior-art register circuitry in orderto practice the present invention.

[0132] Electrical Interface—Input/Output Circuitry

[0133] A block diagram of the preferred input/output circuit foraddress/data/control lines is shown in FIG. 10. This circuitry isparticularly well-suited for use in DRAM devices but it can be used ormodified by one skilled in the art for use in other devices connected tothe bus of this invention. It consists of a set of input receivers 71,72 and output driver 76 connected to input/output line 69 and pad 75 andcircuitry to use the internal clock 73 and internal clock complement 74to drive the input interface. The clocked input receivers take advantageof the synchronous nature of the bus. To further reduce the performancerequirements for device input receivers, each device pin, and thus eachbus line, is connected to two clocked receivers, one to sample the evencycle inputs, the other to sample the odd cycle inputs. By thusde-multiplexing the input 70 at the pin, each clocked amplifier is givena full 2 ns cycle to amplify the bus low-voltage-swing signal into afull value CMOS logic signal. Persons skilled in the art will recognizethat additional clocked input receivers can be used within the teachingsof this invention. For example, four input receivers could be connectedto each device pin and clocked by a modified internal device clock totransfer sequential bits from the bus to internal device circuits,allowing still higher external bus speeds or still longer settling timesto amplify the bus low-voltage-swing signal into a full value CMOS logicsignal.

[0134] The output drivers are quite simple, and consist of a single NMOSpulldown transistor 76. This transistor is sized so that under worstcase conditions it can still sink the 50 mA required by the bus. For 0.8micron CMOS technology, the transistor will need to be about 200 micronslong. Overall bus performance can be improved by using feedbacktechniques to control output transistor current so that the currentthrough the device is roughly 50 mA under all operating conditions,although this is not absolutely necessary for proper bus operation. Anexample of one of many methods known to persons skilled in the art forusing feedback techniques to control current is described in HansSchumacher, et al., “CMOS Subnanosecond True-ECL Output Buffer,” J.Solid State Circuits, Vol. 25 (1), pp. 150-154 (Feb. 1990). Controllingthis current improves performance and reduces power dissipation. Thisoutput driver which can be operated at 500 MHz, can in turn becontrolled by a suitable multiplexer with two or more (preferably four)inputs connected to other internal chip circuitry, all of which can bedesigned according to well known prior art.

[0135] The input receivers of every slave must be able to operate duringevery cycle to determine whether the signal on the bus is a validrequest packet. This requirement leads to a number of constraints on theinput circuitry. In addition to requiring small acquisition andresolution delays, the circuits must take little or no DC power, littleAC power and inject very little current back into the input or referencelines. The standard clocked DRAM sense amp shown in FIG. 11 satisfiesall these requirements except the need for low input currents. When thissense amp goes from sense to sample, the capacitance of the internalnodes 83 and 84 in FIG. 11 is discharged through the reference line 68and input 69, respectively. This particular current is small, but thesum of such currents from all the inputs into the reference lines summedover all devices can be reasonably large.

[0136] The fact that the sign of the current depends upon on theprevious received data makes matters worse. One way to solve thisproblem is to divide the sample period into two phases. During the firstphase, the inputs are shorted to a buffered version of the referencelevel (which may have an offset). During the second phase, the inputsare connected to the true inputs. This scheme does not remove the inputcurrent completely, since the input must still charge nodes 83 and 84from the reference value to the current input value, but it does reducethe total charge required by about a factor of 10 (requiring only a0.25V change rather than a 2.5V change). Persons skilled in the art willrecognize that many other methods can be used to provide a clockedamplifier that will operate on very low input currents.

[0137] One important part of the input/output circuitry generates aninternal device clock based on early and late bus clocks. Controllingclock skew (the difference in clock timing between devices) is importantin a system running with 2 ns cycles, thus the internal device clock isgenerated so the input sampler and the output driver operate as close intime as possible to midway between the two bus clocks.

[0138] A block diagram of the internal device clock generating circuitis shown in FIG. 12 and the corresponding timing diagram in FIG. 13. Thebasic idea behind this circuit is relatively simple. A DC amplifier 102is used to convert the small-swing bus clock into a full-swing CMOSsignal. This signal is then fed into a variable delay line 103. Theoutput of delay line 103 feeds three additional delay lines: 104 havinga fixed delay; 105 having the same fixed delay plus a second variabledelay; and 106 having the same fixed delay plus one half of the secondvariable delay. The outputs 107, 108 of the delay lines 104 and 105drive clocked input receivers 101 and 111 connected to early and latebus clock inputs 100 and 110, respectively. These input receivers 101and 111 have the same design as the receivers described above and shownin FIG. 11. Variable delay lines 103 and 105 are adjusted via feedbacklines 116, 115 so that input receivers 101 and 111 sample the bus clocksjust as they transition. Delay lines 103 and 105 are adjusted so thatthe falling edge 120 of output 107 precedes the falling edge 121 of theearly bus clock, Clock1 53, by an amount of time 128 equal to the delayin input sampler 101. Delay line 108 is adjusted in the same way so thatfalling edge 122 precedes the falling edge 123 of late bus clock, Clock254, by the delay 128 in input sampler 111.

[0139] Since the outputs 107 and 108 are synchronized with the two busclocks and the output 73 of the last delay line 106 is midway betweenoutputs 107 and 108, that is, output 73 follows output 107 by the sameamount of time 129 that output 73 precedes output 108, output 73provides an internal device clock midway between the bus clocks. Thefalling edge 124 of internal device clock 73 precedes the time of actualinput sampling 125 by one sampler delay. Note that this circuitorganization automatically balances the delay in substantially alldevice input receivers 71 and 72 (FIG. 10), since outputs 107 and 108are adjusted so the bus clocks are sampled by input receivers 101 and111 just as the bus clocks transition.

[0140] In the preferred embodiment, two sets of these delay lines areused, one to generate the true value of the internal device clock 73,and the other to generate the complement 74 without adding any inverterdelay. The dual circuit allows generation of truly complementary clocks,with extremely small skew. The complement internal device clock is usedto clock the ‘even’ input receivers to sample at time 127, while thetrue internal device clock is used to clock the ‘odd’ input receivers tosample at time 125. The true and complement internal device clocks arealso used to select which data is driven to the output drivers. The gatedelay between the internal device clock and output circuits driving thebus is slightly greater than the corresponding delay for the inputcircuits, which means that the new data always will be driven on the busslightly after the old data has been sampled.

[0141] DRAM Column Access Modification

[0142] A block diagram of a conventional 4 MBit DRAM 130 is shown inFIG. 15. The DRAM memory array is divided into a number of subarrays150-157, for example, 8. Each subarray is divided into arrays 148, 149of memory cells. Row address selection is performed by decoders 146. Acolumn decoder 147A, 147B, including column sense amps on either side ofthe decoder, runs through the core of each subarray. These column senseamps can be set to precharge or latch the most-recently stored value, asdescribed in detail above. Internal I/O lines connect each set ofsense-amps, as gated by corresponding column decoders, to input andoutput circuitry connected ultimately to the device pins. These internalI/O lines are used to drive the data from the selected bit lines to thedata pins (some of pins 131-145), or to take the data from the pins andwrite the selected bit lines. Such a column access path organized byprior art constraints does not have sufficient bandwidth to interfacewith a high speed bus. The method of this invention does not requirechanging the overall method used for column access, but does changeimplementation details. Many of these details have been implementedselectively in certain fast memory devices, but never in conjunctionwith the bus architecture of this invention.

[0143] Running the internal I/O lines in the conventional way at highbus cycle rates is not possible. In the preferred method, several(preferably 4) bytes are read or written during each cycle and thecolumn access path is modified to run at a lower rate (the inverse ofthe number of bytes accessed per cycle, preferably ¼ of the bus cyclerate). Three different techniques are used to provide the additionalinternal I/O lines required and to supply data to memory cells at thisrate. First, the number of I/O bit lines in each subarray runningthrough the column decoder 147 is increased, for example, to 16, eightfor each of the two columns of column sense amps and the column decoderselects one set of columns from the “top” half 148 of subarray 150 andone set of columns from the “bottom” half 149 during each cycle, wherethe column decoder selects one column sense amp per I/O bit line.Second, each column I/O line is divided into two halves, carrying dataindependently over separate internal I/O lines from the left half 147Aand right half 147B of each subarray (dividing each subarray intoquadrants) and the column decoder selects sense amps from each right andleft half of the subarray, doubling the number of bits available at eachcycle. Thus each column decode selection turns on n column sense amps,where n equals four (top left and right, bottom left and rightquadrants) times the number of I/O lines in the bus to each subarrayquadrant (8 lines each×4=32 lines in the preferred implementation).Finally, during each RAS cycle, two different subarrays, e.g. 157 and153, are accessed. This doubles again the available number of I/O linescontaining data. Taken together, these changes increase the internal I/Obandwidth by at least a factor of 8. Four internal buses are used toroute these internal I/O lines. Increasing the number of I/O lines andthen splitting them in the middle greatly reduces the capacitance ofeach internal I/O line which in turn reduces the column access time,increasing the column access bandwidth even further.

[0144] The multiple, gated input receivers described above allow highspeed input from the device pins onto the internal I/O lines andultimately into memory. The multiplexed output driver described above isused to keep up with the data flow available using these techniques.Control means are provided to select whether information at the devicepins should be treated as an address, and therefore to be decoded, orinput or output data to be driven onto or read from the internal I/Olines.

[0145] Each subarray can access 32 bits per cycle, 16 bits from the leftsubarray and 16 from the right subarray. With 8 I/O lines persense-amplifier column and accessing two subarrays at a time, the DRAMcan provide 64 bits per cycle. This extra I/O bandwidth is not neededfor reads (and is probably not used), but may be needed for writes.Availability of write bandwidth is a more difficult problem than readbandwidth because over-writing a value in a sense-amplifier may be aslow operation, depending on how the sense amplifier is connected to thebit line. The extra set of internal I/O lines provides some bandwidthmargin for write operations.

[0146] Persons skilled in the art will recognize that many variations ofthe teachings of this invention can be practiced that still fall withinthe claims of this invention which follow.

What is claimed is:
 1. A memory subsystem comprising two memory devicesconnected in parallel to a bus, said bus including a plurality of buslines for carrying substantially all address, data and controlinformation needed by said memory devices, said control informationincluding device-select information, said bus containing substantiallyfewer bus lines than the number of bits in a single address, and saidbus carrying device-select information without the need for separatedevice-select lines connected directly to individual memory devices. 2.The memory subsystem of claim 1 wherein said bus contains at least 8 buslines adapted to carry at least 16 address bits and at least 8 databits.
 3. The memory subsystem of claim 1 wherein said bus also includesparallel lines for clock and power.
 4. A system comprising a memorysubsystem of claim 1 wherein each bus of said memory subsystem isconnected to its own transceiver device, a transceiver bus connectingsaid transceiver devices, and a means for transferring informationbetween each of said buses of said memory subsystems and saidtransceiver bus, whereby memory subsystems may be integrated into alarger system having more memory than an individual memory subsystem. 5.The system of claim 4 having a plurality of memory subsystems.
 6. Thesystem of claim 4 further comprising a master device connected to saidtransceiver bus.
 7. The system of claim 6 wherein said master device isselected from the group consisting of a central processing unit, afloating point unit and a direct memory access unit.
 8. The system ofclaim 4 further comprising a peripheral device connected to thetransceiver bus, said peripheral device adapted for connection to otherdevices not on the bus.
 9. The system of claim 8 wherein said peripheraldevice is selected from the group consisting of an I/O interface port, avideo controller and a disk controller.
 10. The system of claim 5wherein said transceiver bus is in a different plane than the plane ofthe bus of each of said memory subsystems.
 11. The system of claim 5wherein the bus of each memory subsystem lies substantially in asubsystem bus plane and said transceiver bus lies substantially in aplane orthogonal to said subsystem bus plane.
 12. The system of claim 4having at least two transceiver buses, each transceiver bus having aplurality of memory subsystem buses connected through a firsttransceiver to said transceiver bus, each of said transceiver busesbeing further connected to a second transceiver adapted to interface toa second-order transceiver bus, whereby each transceiver bus isconnected through said second transceiver to form a second-ordertransceiver bus unit.
 13. A semiconductor subsystem bus forinterconnecting semiconductor devices comprising a plurality ofsemiconductor devices connected in parallel to a bus, at least one ofsaid semiconductor devices being a memory device or a transceiver devicewhich in turn is connected to a memory subsystem, said bus including aplurality of bus lines for carrying substantially all address, data andcontrol information needed by said semiconductor devices, said controlinformation including semiconductor device-select information, said buscontaining substantially fewer bus lines than the number of bits in asingle address, and said bus carrying device-select information withoutthe need for separate device-select lines connected directly toindividual semiconductor devices, and at least one modifiable registerin each of the semiconductor devices on said bus, said modifiableregisters being accessible from said bus, whereby the subsystem can beconfigured using signals transmitted on said bus.
 14. The semiconductorsubsystem bus of claim 13 wherein one type of modifiable register is anaccess-time register designed to store a time delay after which a devicemay take some specified action on said bus.
 15. The semiconductorsubsystem bus of claim 13 further comprising a semiconductor devicehaving at least two access-time registers and one of said access-timeregisters is permanently programmed to contain a fixed value and atleast one of said access-time registers can be modified by informationcarried on said bus.
 16. The semiconductor subsystem bus of claim 13further comprising a memory device having at least one discrete memorysection and also having a modifiable address register adapted to storememory address information which corresponds to each said discretememory section.
 17. The semiconductor subsystem bus of claim 16 whereinsaid memory address information comprises a pointer to said discretememory section.
 18. The semiconductor subsystem bus of claim 16 whereinsaid discrete memory section has a top and a bottom and said memoryaddress information comprises pointers to said top and said bottom. 19.The semiconductor subsystem bus of claim 16 wherein said memory addressinformation comprises a pointer to said discrete memory section and arange value indicating the size of said discrete memory section.
 20. Thesemiconductor subsystem bus of claim 16 wherein said address registersof each of said discrete memory sections of each of said memory devicesconnected to said bus are set to contain memory address information thatis different for each discrete memory section and such that the highestmemory address in each discrete memory section is one less than thelowest memory address in another discrete memory section, whereby memorymay be organized into one or a small number of contiguous memory blocks.21. The semiconductor subsystem bus of claim 16 further comprising ameans for testing each of said discrete memory sections of each of saidmemory devices for proper function, and for each non-functional discretememory section, a means for setting at least one address register whichcorresponds to said discrete memory section to indicate that saiddiscrete memory section is non-functional, for each functional discretememory section, a means for setting at least one address register whichcorresponds to said discrete memory section to contain suchcorresponding address information.
 22. The semiconductor subsystem busof claim 21 wherein said address registers corresponding to saiddiscrete memory sections are set to provide one contiguous memory blockwithin the subsystem.
 23. The semiconductor subsystem bus of claim 13wherein one of said modifiable registers is a device identificationregister which can be modified to contain a value unique to thatsemiconductor device.
 24. The semiconductor subsystem bus of claim 23wherein said device identification register is set to contain a uniquevalue which is a function of the physical position of that semiconductordevice either along said bus or in relationship to other semiconductordevices or said bus.
 25. A bus subsystem comprising two semiconductordevices connected in parallel to a bus, wherein one of saidsemiconductor devices is,a master device, said master device including ameans for initiating bus transactions, said bus including a plurality ofbus lines for carrying substantially all address, data and controlinformation needed by said devices, said control information includingdevice-select information, said bus containing substantially fewer linesthan the number of bits in a single address, and said bus carryingdevice-select information without the need for separate device-selectlines connected directly to individual devices on said bus, whereby saidmaster device initiates bus transactions which transfer informationbetween said semiconductor devices on said bus.
 26. The bus subsystem ofclaim 25 wherein one of said semiconductor devices is a memory deviceconnected to said bus, said memory device having at least one discretememory section and also having a modifiable address register adapted tostore memory address information which corresponds to each said discretememory section.
 27. The bus subsystem of claim 26 wherein one of saidsemiconductor devices comprises a transceiver device connected inparallel to said bus and connected in parallel to a memory device on abus other than said bus.
 28. The bus subsystem of claim 26 furtherincluding a means for said master device to request said memory deviceto prepare for a bus transaction by sending a request packet along saidbus, said memory device and said master device each having adevice-internal means to prepare to begin said bus transaction during adevice-internal phase and further having a bus access means to effectsaid bus transaction during a bus access phase, said request packetincluding a sequence of bytes containing address and controlinformation, said control information including information about therequested bus transaction and about the access time, which correspondsto a number of bus cycles, which needs to intervene before beginningsaid bus-access phase, and said address information pointing to at leastone memory location within one of said discrete memory sections of saidmemory device.
 29. The bus subsystem of claim 28 wherein said memorydevice includes a means to read said control information and initiatesaid device-internal means at a time so as to complete saiddevice-internal phase within said access time and begin said bus accessphase after said number of bus cycles.
 30. The bus subsystem of claim 28wherein said control information comprises an op code.
 31. The bussubsystem of claim 30 wherein said memory device includes senseamplifiers adapted to hold a bit of information or to precharge after aselected time and a means to transfer a data block during a data blocktransfer either reading data from said memory device or writing datainto said memory device, and wherein said op code instructs said memorydevice to activate a response means, said response means including ameans to initiate a data block transfer, select the size of said datablock, select the time to initiate said data block transfer, access acontrol register, including reading from or writing to said controlregister, precharge said sense amplifiers after each of said data blocktransfers is complete, hold a bit of information in each of said senseamplifiers after each of said data block transfers is complete, orselect normal or page-mode access.
 32. The bus subsystem of claim 31wherein said data block transfer comprises a read from or a write tomemory within a single memory device.
 33. The bus subsystem of claim 28further comprising a means for said master device to send controlinformation to a specific one of said semiconductor devices on said busby including in said request packet a device identification numberunique to said semiconductor device.
 34. The bus subsystem of claim 28further comprising a means for said master device to send controlinformation to a selected one of said discrete memory portions byincluding in said request packet a specific memory address.
 35. The bussubsystem of claim 28 further comprising a means for said master deviceto send control information to substantially all semiconductor deviceson said bus by including in said request packet a special deviceidentification number which is recognized by said semiconductor devices.36. The bus subsystem of claim 28 wherein said control informationspecifies directly or indirectly the number of bus cycles for saidmaster device and said memory device to wait before beginning said busaccess phase.
 37. The bus subsystem of claim 36 wherein, for a datablock transfer, said master device and said memory device use the sameaccess time and same data block size regardless of whether said datablock transfer is a read or write operation.
 38. The bus subsystem ofclaim 28 wherein said control information further includes a block-sizevalue that encodes and specifies the size of the block of data to betransferred.
 39. The bus subsystem of claim 38 wherein said block-sizevalue is encoded as a linear value for relatively small block sizesvalues and is encoded as a logarithmic value for relatively larger blocksizes.
 40. The bus subsystem of claim 38 wherein said block-size valueis encoded using four bits, and where the encoded value is Encoded ValueBlock Size (Bytes) 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 16 10 32 11 6412 128 13 256 14 512 15 1024


41. The bus subsystem of claim 26 wherein said memory device is a DRAMdevice containing a plurality of sense amplifiers, a means to hold saidsense amplifiers in an unmodified state after a read or write operation,leaving the device in page mode, a means to precharge said senseamplifiers and a means for selecting whether to precharge said senseamplifiers or to hold said sense amplifiers in an unmodified state. 42.The bus subsystem of claim 28 wherein said request packet comprises aneven number of bytes.
 43. The bus subsystem of claim 28 furtherincluding a means for generating and controlling a plurality of buscycles, during which said bus carries said address, data and controlinformation, and wherein alternate said bus cycles are designated oddcycles and even cycles, respectively, and wherein said request packetbegins only on an even cycle.
 44. The bus subsystem of claim 28 furtherincluding a means for generating ECC information corresponding to ablock of data and a means for using said ECC information to correcterrors in storing or reading said block of data, wherein said ECCinformation may be stored separately from said block of data.
 45. Thebus subsystem of claim 44 further comprising at least two of said memorydevices wherein said ECC information and said corresponding block ofdata are stored in a first and a second said memory device,respectively, and said master device includes a means to write or readsaid block of data with error correction by sending separate ones ofsaid request packets for said ECC information and for said correspondingblock of data.
 46. A bus subsystem comprising a memory device and amaster device connected in parallel on a bus, a means for said masterdevice to send a request packet and initiate a bus transaction and ameans for said master device to keep track of current and pending bustransactions, said bus including a plurality of bus lines for carryingsubstantially all address, data and control information needed by saidmemory devices, said bus containing substantially fewer lines than thenumber of bits in a single address, and said bus carrying device-selectinformation without the need for separate device-select lines connecteddirectly to individual devices on said bus, whereby said master deviceinitiates bus transactions which transfer information between devices onsaid bus and collisions on said bus are avoided because said masterdevice avoids initiating bus transactions which would conflict withcurrent or pending bus transactions.
 47. The bus subsystem of claim 46having at least two of said master devices and including a collisiondetecting means whereby a first said master device sending a first saidrequest packet can detect a second said master device sending one ofsaid colliding request packets, where one of said said colliding requestpacket may be sent simultaneous with the initial sending of oroverlapping the sending of said first request packet, and an arbitrationmeans whereby said first and said second master devices select apriority order in which each of said master devices will be allowed toaccess said bus sequentially.
 48. The bus subsystem of claim 47 whereineach of said master devices has a master ID number and each of saidrequest packets includes a master ID position which is a predeterminednumber of bits in a predetermined position in said request packet, andwherein said collision detection means comprises a means included ineach master device for sending a request packet including said master IDnumber of said master device in said master ID position of said requestpacket and a means to detect a collision and invoke said arbitrationmeans if any master device detects any other master ID number in saidmaster ID position.
 49. The bus subsystem of claim 47 wherein each ofsaid master devices includes a means for sending a request packet, ameans for driving a selected bus line or lines during at least oneselected bus cycle while said request packet is being sent, a means formonitoring said selected bus line or lines to see if a said masterdevice is sending a colliding request packet and a means for informingall other master devices that a collision has occurred and for invokingsaid arbitration means.
 50. The bus subsystem of claim 47 wherein eachof said master devices includes a means, when sending a request packet,to drive a selected bus line or lines with a certain current during atleast one selected bus cycle, a means for monitoring said selected busline or lines for a greater than normal current to see if another masterdevice is driving that line or lines, a means for detecting said greaterthan normal current, and a means for informing all said master devicesthat a collision has occurred and for invoking said arbitration means.51. The bus subsystem of claim 47 wherein said arbitration meanscomprises a means for initiating an arbitration cycle, a means forallocating a single bus line to each master device during at least oneselected bus cycle relative to the start of said arbitration cycle, ameans for allocating each master device to a single bus line during oneof said selected bus cycles if there are more master devices thanavailable bus lines, a means for each of said master devices which senta colliding request packet to drive said bus line allocated to saidmaster device during said selected bus cycle, and a means in at leastone of said master devices for storing information about which masterdevices sent a colliding request packet, whereby said master devices canmonitor selected bus lines during said arbitration cycle and identifyeach said master device which sent a colliding request packet.
 52. Thebus subsystem of claim 47 wherein said arbitration means comprises ameans included in a first one of said master devices which sentcolliding request packets for identifying each of said master deviceswhich sent colliding request packets, a means for assigning a priorityto each said master device which sent a colliding request packet, and ameans for allowing each said master device which sent a collidingrequest packet to access the bus sequentially according to thatpriority.
 53. The bus subsystem of claim 52 wherein said priority isbased on the physical location of each of said master devices.
 54. Thebus subsystem of claim 52 wherein said priority is based on said masterID number of said master devices.
 55. The bus subsystem of claim 52wherein each of said master devices includes a means, when sending acolliding request packet, for deciding which master device can send thenext request packet in what order or at what time, whereby no masterdevice may send a new request packet until responses to each pendingrequest packet have been completed or scheduled.
 56. A bus subsystemcomprising a plurality of semiconductor devices connected in parallel toa bus, said bus including a plurality of bus lines for carryingsubstantially all address, data and control information needed by saidsemiconductor devices, said control information including device-selectinformation, said bus containing substantially fewer lines than thenumber of bits in a single address, said bus carrying said device-selectinformation without the need for separate device-select lines connecteddirectly to individual semiconductor devices, said semiconductor devicesincluding a reset means having an input and an output, the output of thereset means of one semiconductor device being connected to the input ofthe reset means of the next semiconductor device in series.
 57. The bussubsystem of claim 56 further including system reset means comprising ameans for generating a first and a second reset signal, a means forpassing said first reset signal to a first of said semiconductor devicesand then to subsequent ones of said semiconductor devices in series anda means for passing a second reset signal to said first semiconductordevice and then to said subsequent semiconductor devices in series, saidbus subsystem including one of said semiconductor devices containing adevice identification register adapted to contain a number unique tosaid semiconductor device within said bus subsystem, a deviceidentification register setting means, and a device reset means forresetting said semiconductor device to some desired, known reset statein response to said first reset signal and for setting said deviceidentification register in response to said second reset signal, wherebysaid bus subsystem can be reset to a known reset state with a uniquedevice identification value in said device identification register ofeach of said semiconductor devices.
 58. The bus subsystem of claim 57wherein said desired, known reset state is where all registers in thesemiconductor device are cleared and the state machines are reset. 59.The bus subsystem of claim 57 wherein said device identificationregister setting means comprises a means for detecting said second resetsignal, a means for reading a device identification number from said buslines at a specific time relative to said second reset signal and ameans for storing said device identification number in said deviceidentification register of said semiconductor device.
 60. The bussubsystem of claim 57 wherein said second reset signal comprisesmultiple pulse sequences and wherein said device identification settingmeans includes a means for interpreting said pulse sequences as a deviceidentification number and a means for storing said device identificationnumber in said device identification register of said semiconductordevice.
 61. The bus subsystem of claim 57 wherein said device resetmeans comprises an n-stage shift register capable of storing n-bitvalues, wherein said device reset means interprets a specific value insaid shift register as said first reset signal and interprets a specificvalue in said shift register as said second reset signal.
 62. The bussubsystem of claim 57 wherein one of said semiconductor devices is amaster device, said master device including a means for generating saidfirst and said second reset signals.
 63. The bus subsystem of claim 57wherein one of said semiconductor devices is a master device, saidmaster device including a master ID register, a means for assigning amaster ID number to said master device and a means for storing saidmaster ID number in said master ID register.
 64. The bus subsystem ofclaim 63 further comprising a second one of said master devices, and ameans for a first one of said master devices to assign a master IDnumber to substantially all other said master devices, whereby saidfirst master device assigns one of said master ID numbers to each ofsaid master devices on said bus subsystem and each said master devicestores said assigned master ID number in said master ID register. 65.The bus subsystem of claim 57 wherein one of said semiconductor devicesincludes a device-type register adapted to contain an identifiercharacteristic of that type of semiconductor device, and one or moremodifiable registers, at least one of which is an access-time registeradapted for storing access times.
 66. The bus subsystem of claim 65wherein one of said semiconductor devices is a master device having ameans for selecting a semiconductor device, a means for reading saiddevice-type register of said selected semiconductor device, a means fordetermining the device type of said selected semiconductor device, ameans for determining access-time values appropriate for said selectedsemiconductor device and for storing said access-time values in saidaccess-time registers of said selected semiconductor device, and a meansfor selecting and storing other values appropriate for said selectedsemiconductor device in corresponding registers of said selectedsemiconductor device, whereby said master device can select asemiconductor device, determine what type it is, and set saidaccess-time and other registers to contain appropriate values.
 67. Thebus subsystem of claim 66 further comprising a memory device having atleast one discrete memory section and at least one modifiable addressregister adapted to store memory address information which correspondsto each of said discrete memory sections, and said master device furthercomprising a means for selecting and testing each of said discretememory sections and a means for storing address information in saidaddress registers corresponding to each of said discrete memorysections, whereby said master device can test all said discrete memorysections and assign unique address values thereto.
 68. A bus subsystemcomprising two semiconductor devices connected in parallel to a bus, oneof said semiconductor devices being a master device, said bus includinga plurality of bus data lines for carrying substantially all address,data and control information needed by said semiconductor devices, saidcontrol information including device-select information, said buscontaining substantially fewer of said bus data lines than the number ofbits in a single address, and said bus carrying device-selectinformation without the need for separate device-select lines connecteddirectly to individual semiconductor devices, wherein all of said busdata lines are terminated transmission lines and all of said address,data and control information is carried on said bus data lines as asequential series of bits in the form of low-voltage-swing signals. 69.The bus subsystem of claim 68 further comprising a semiconductor deviceincluding a current-mode driver connected to drive one of said bus datalines.
 70. The bus subsystem of claim 69 further comprising asemiconductor device having a means to measure the voltage of saidlow-voltage-swing signals on a selected one of said bus data lines,whereby said semiconductor device can determine whether zero, one, ormore than one of said current-mode drivers are driving said selected busdata line.
 71. The bus subsystem of claim 70 further comprising asemiconductor device having a plurality of input receivers connected toone of said bus data lines, and a selection means for selecting saidinput receivers one by one to sense and store, one at a time, the bitsof said sequential series of bits.
 72. The bus subsystem of claim 70further comprising a semiconductor device having two input receiversconnected to one of said bus data lines.
 73. A bus subsystem comprisingtwo semiconductor devices connected in parallel to a bus having a firstand a second end, said bus including a bus clock line, said bus clockline having first and second ends corresponding to said first and secondends of said bus, respectively, a clock generator connected to saidfirst end of said bus clock line to generate early bus clock signalswith a normal rise time, and signal return means at said second end ofsaid bus clock line to return said early bus clock signals to said firstend of said bus as corresponding late bus clock signals, whereby each ofsaid early bus clock signals will propagate from said clock generatoralong said clock line starting from said first end to said second end ofsaid bus and then return at a later time to said first end of said busas a corresponding late bus clock signal, whereby each semiconductordevice on said bus can detect said early bus clock signals and saidcorresponding late bus clock signals.
 74. The bus subsystem of claim 73further comprising a first and a second said bus clock line having firstand second ends at said first and said second ends of said bus,respectively, wherein said signal return means directly connects saidsecond ends of said first and said second bus clock lines whereby eachof said early bus clock signals will propagate from said clock generatorat said first end of said bus along said first bus clock line to saidsecond end of said bus and then return on said second bus clock line tosaid first end of said bus as one of said corresponding late bus clocksignals.
 75. The bus subsystem of claim 73 wherein said signal returnmeans comprises said first bus clock line without a line terminator atsaid second end thereof whereby each of said early bus clock signalsreaching said second end of said first bus clock line will be reflectedback along said first bus clock line as said corresponding late busclock signals.
 76. The bus subsystem of claim 73 further comprising ameans for operating said bus in bus cycles timed to have a certain buscycle frequency and a corresponding bus cycle period and a means foroperating said clock generator with a period of twice the bus cycleperiod.
 77. The bus subsystem of claim 76 wherein said bus cyclefrequency is greater than approximately 50 MHz and less than or equal toapproximately 500 MHz.
 78. The bus subsystem of claim 73 furtherincluding a semiconductor device having an internal device clockgenerating means to derive the midpoint time between said early andcorresponding late bus clock signals and to generate an internal deviceclock synchronized to said midpoint time.
 79. The bus subsystem of claim73 further including a semiconductor device having a low-skew clockgenerator circuit comprising a first delay line having an input, anoutput and a basic delay and means for synchronizing the output of saidfirst delay line with said early bus clock signal, a second delay linehaving said basic delay plus a variable delay, said second delay linehaving an output and a means for synchronizing the output of said seconddelay line with said late bus clock signal, and a third delay linehaving a third delay and a means to set said third delay midway betweenthe delays of said first and second delay lines, said third delay linehaving an output which provides an internal device clock signalsynchronized to a time halfway between said early and said late busclock signals.
 80. The bus subsystem of claim 73 wherein said early andsaid late bus clock signals are low-voltage-swing signals thattransition cyclically between low and high logical values, and furtherincluding a semiconductor device having a low-skew clock generatorcircuit comprising a DC amplifier to convert said early and said latebus clock signals into full-swing logic signals, a first variable delayline having a first variable delay and an input and an output, the inputof said first variable delay line being connected to said DC amplifier afirst, a second and a third additional delay line, each having an inputand an output, the input of each of said additional delay lines beingconnected to the output of said first delay line, said first additionaldelay line having a fixed delay, said second additional delay linehaving said fixed delay plus a second variable delay, and said thirdadditional delay line having said fixed delay plus one half of saidsecond variable delay, a first clocked input receiver connected tosample said early bus clock signal and gated by said output of saidfirst additional delay line, a means for adjusting said first variabledelay so said first clocked input receiver samples said early bus clocksignal just as said early bus clock signal transitions, a second clockedinput receiver connected to sample said late bus clock signal and gatedby said output of said second additional delay line, a means foradjusting said second variable delay so said second clocked inputreceiver samples said late bus clock signal just as said late bus clocksignal transitions, whereby said output of said third additional delayline is synchronized to a time halfway between said outputs of saidfirst and said second additional delay lines, and said output of saidthird additional delay line provides an internal device clock signal.81. The bus subsystem of claim 80 further comprising a semiconductordevice having a first one of said low-skew clock generator circuitswhich generates a “true” internal device clock signal and a second oneof said low-skew clock generator circuits connected to generate a“complement” internal device clock signal synchronized with but oppositein logical value to said “true” internal device clock signal.
 82. A DRAMdevice designed to be connected to an external bus having a plurality ofbus lines for carrying substantially all address, data and controlinformation needed by said DRAM device as a sequential series of bits,said control information including device-select information, saidexternal bus containing substantially fewer said bus lines than thenumber of bits in a single address, and said bus carrying device-selectinformation without the need for separate device-select lines connecteddirectly to said DRAM device, said DRAM device comprising an array ofmemory cells connected in rows and columns, each of said memory cellsadapted to store one of said bits, a row address selection means forselecting one of said rows, a column sense amp connected to each of saidcolumns, each of said column sense amps adapted to latch one of saidbits as a binary logical value or to precharge to a selected state, acolumn decoding means connected to each of said column sense amps forselecting a plurality of said column sense amps for inputting one ofsaid bits to or outputting one of said bits from said memory cells, aninternal I/O bus having a plurality of internal I/O lines wherein eachof said internal I/O lines is connected to a plurality of said columnsense amps, and a plurality of bus connection means designed to connectsaid internal I/O lines to said external bus, whereby a selected bit ofsaid sequential series of bits can be transferred from said external busto a selected one of said memory cells or said bit contained in aselected one of said memory cells can be transferred to said externalbus.
 83. The DRAM device of claim 82 further comprising an output driverconnected to one said bus connection means, an output multiplexer havingan output connected to said output driver and a plurality of inputs,each of said inputs being connected to one of said internal I/O lines,and a control means to select whether said output driver can drive saidexternal bus, whereby a plurality of memory cells are selected usingsaid row address selection means and said column decoding means and aplurality of bits contained in said plurality of memory cells are outputthrough said column sense amps to said internal I/O bus to said outputmultiplexer to said output driver to said external bus.
 84. The DRAMdevice of claim 82 further comprising a plurality of input receiversconnected to one of said bus data lines and to said internal I/O bus, aselection means for selecting said input receivers one by one to senseand store, one at a time, the bits of said sequential series of bits,and a control means to select whether an input receiver can drive saidinternal I/O bus, whereby a bit of said sequential series of bits isinput from said external bus through one of said input receivers to oneof said internal I/O lines to one of said column sense amps to one ofsaid memory cells.
 85. The DRAM device of claim 82 further comprising afirst and a second half-array of said memory cells wherein each said rowof said array of said memory cells is subdivided into two parts, a firstand a second one of said internal I/O buses connected to said columnsense amps in said first and said second half-arrays, respectively, anda column decoder means to gate selected ones of said column sense ampsconnected to said memory cells in a selected row of said first and saidsecond half-arrays simultaneously.
 86. The DRAM device of claim 85wherein said column decoder means selects sixteen column sense amps at atime.
 87. The DRAM device of claim 82 wherein said external bus operatesat a certain speed and wherein said DRAM device includes four of saidinternal I/O buses, each of which operates at one-fourth the speed ofsaid external bus.
 88. The DRAM device of claim 82 further comprising ameans for precharging one of said column sense amps to a prechargedstate from which a binary logical value can quickly be loaded into saidcolumn sense amp, if said column sense amp contains a binary logicalvalue, a means for latching the logical value currently contained insaid column sense amp and a means for instructing said DRAM device toprecharge said column sense amp or latch said binary logical value insaid column sense amp.
 89. The DRAM device of claim 88 furthercomprising a means for instructing said DRAM device to precharge saidcolumn sense amp without further instruction whenever said row addressselection means selects a different one of said rows.
 90. The DRAMdevice of claim 88 further comprising a means for instructing said DRAMdevice to precharge said column sense amp without further instruction ata first or a second preselected time after latching the latest saidbinary logical value, said first preselected time being long enough forsaid DRAM to latch said binary logical value into said column sense ampand transfer said binary logical value into memory or onto one of saidinternal I/O lines, and said second preselected time being a variablewhich can be stored in said DRAM device whereby said DRAM can latch abinary logical value into said column sense amp for transferring saidbinary logical value into or out of a selected said memory cell, thenprecharge to allow a faster subsequent read or write.
 91. A packagecontaining a semiconductor die having a side, circuitry and a pluralityof connecting areas positioned along or near said side, spaced at aselected pitch and connected to said circuitry, said package comprisinga plurality of bus connecting means for connecting to a plurality ofexternal bus lines, each of said external bus lines corresponding to oneof said connecting areas, each of said bus connecting means beingpositioned on a first side of said package, connected to one saidexternal bus line and to said corresponding connecting area on saidsemiconductor die, and spaced at a pitch substantially identical to saidselected pitch of said connecting areas, whereby each of said externalbus lines can be connected to said corresponding connecting area on saidsemiconductor die by bus connection means positioned along a single sideof said package.
 92. The package of claim 91 further comprising aplurality of said bus connecting means wherein each of said busconnecting means includes a pin adapted for connection to one of saidexternal bus lines and a wire connecting said pin to one of saidconnecting areas on said semiconductor die, said wire having aneffective lead length less than about 4 millimeters and wherein theeffective lead length of said wire of each of said bus connection meansfor said package is approximately equal.
 93. A plurality of packages ofclaim 91 wherein at least two of said semiconductor die are memorydevices, each of said packages being generally flat, having a top and abottom, and wherein said packages are physically secured adjacent andparallel to each other in a stack, where a first one of said packages isadjacent to a second one of said packages in said stack, said top ofsaid first package is substantially aligned with said bottom of saidsecond package, and said bus connecting means of each of said packagesare substantially aligned and are lying substantially in a plane. 94.The plurality of packages of claim 93 further comprising a plurality ofstacks wherein each of said bus connecting means can be electricallyconnected to corresponding said bus connecting means in each of saidstacks.
 95. A semiconductor device capable of use in a semiconductor busarchitecture including a plurality of semiconductor devices connected inparallel to a bus wherein said bus includes a plurality of bus lines forcarrying substantially all address, data, control and device-selectinformation needed by said semiconductor device for communication withsubstantially every other semiconductor device connected to said bus,and has substantially fewer bus lines than the number of bits in asingle address, and carries device-select information for saidsemiconductor device without the need for a separate device-select lineconnected directly to said individual semiconductor device, saidsemiconductor device comprising connection means adapted to connect saidsemiconductor device to said bus, and at least one modifiableidentification register accessible to said bus through said connectionmeans, whereby data may be transmitted to said register via said bus andenable said device thereafter to be uniquely identified.
 96. Thesemiconductor device of claim 95 wherein said semiconductor device is amemory device which connects substantially only to said bus and sendsand receives substantially all address, data and control informationover said bus.
 97. A semiconductor device capable of use in asemiconductor bus architecture including a plurality of semiconductordevices connected in parallel to a bus wherein said bus includes aplurality of bus lines for carrying substantially all address, data,control and device-select information needed by said semiconductordevice for communication with substantially every other semiconductordevice connected to said bus, and has substantially fewer bus lines thanthe number of bits in a single address, and carries device-selectinformation for said semiconductor device without the need for aseparate device-select line connected directly to said individualsemiconductor device, said semiconductor device comprising connectionmeans adapted to connect said semiconductor device to said bus, and atleast one modifiable register to hold device address information, saidmodifiable register accessible to said bus through said connectionmeans, whereby data may be transmitted to said register via said buswhich enables said device thereafter to respond to a predetermined rangeof addresses.
 98. The semiconductor device of claim 97 wherein saidsemiconductor device is a memory device which connects substantiallyonly to said bus and sends and receives substantially all address, dataand control information over said bus.
 99. The semiconductor device ofclaim 98 wherein said memory device has at least one discrete memorysection and also has at least one modifiable address register adapted tostore memory address information which corresponds to each said discretememory section.
 100. The semiconductor device of claim 99 wherein saidmemory address information comprises a pointer to said discrete memorysection.
 101. The semiconductor device of claim 100 wherein saiddiscrete memory section has a top and a bottom and said memory addressinformation comprises pointers to said top and said bottom.
 102. Thesemiconductor device of claim 100 wherein said memory addressinformation comprises a pointer to said discrete memory section and arange value indicating the size of said discrete memory section.
 103. Asemiconductor device capable of use in a semiconductor bus architectureincluding a plurality of semiconductor devices connected in parallel toa bus wherein said bus includes a plurality of bus lines for carryingsubstantially all address, data and control information needed by saidsemiconductor device for communication with substantially every othersemiconductor device connected to said bus, and has substantially fewerbus lines than the number of bits in a single address, saidsemiconductor device comprising connection means adapted to connect saidsemiconductor device to said bus, and at least one modifiableaccess-time register accessible to said bus through said connectionmeans, whereby data may be transmitted to said register via said buswhich establishes a predetermined amount of time that said semiconductordevice thereafter must wait before using said bus in response to arequest.
 104. The semiconductor device of claim 103 wherein saidsemiconductor device is a memory device which connects substantiallyonly to said bus and sends and receives substantially all address, dataand control information over said bus.
 105. The semiconductor device ofclaim 103 further comprising at least two access-time registers and oneof said access-time registers is permanently programmed to contain afixed value and at least one of said access-time registers can bemodified by information carried on said bus.
 106. A semiconductor devicecapable of use in a semiconductor bus architecture including a pluralityof semiconductor devices connected in parallel to a bus wherein said busincludes a plurality of bus lines for carrying substantially alladdress, data, control and device-select information needed by saidsemiconductor device for communication with substantially every othersemiconductor device connected to said bus, and has substantially fewerbus lines than the number of bits in a single address, and carriesdevice-select information for said semiconductor device without the needfor a separate device-select line connected directly to said individualsemiconductor device, and wherein each said bus line is a terminatedtransmission line, said semiconductor device comprising connection meansadapted to connect said semiconductor device to said bus, and a bus linedriver capable of producing a low-voltage-swing signal on one of saidterminated transmission lines.
 107. The semiconductor device of claim106 wherein said semiconductor device is a memory device which connectssubstantially only to said bus and sends and receives substantially alladdress, data and control information over said bus.
 108. Asemiconductor device capable of use in a semiconductor bus architectureincluding a plurality of semiconductor devices connected in parallel toa bus wherein said bus includes a plurality of bus lines for carryingsubstantially all address, data, control and device-select informationneeded by said semiconductor device for communication with substantiallyevery other semiconductor device connected to said bus, and hassubstantially fewer bus lines than the number of bits in a singleaddress, and carries device-select information for said semiconductordevice without the need for a separate device-select line connecteddirectly to said individual semiconductor device, said bus furtherincluding at least one bus clock line for carrying early and late busclock signals, said semiconductor device comprising connection meansadapted to connect said semiconductor device to said bus, and aninternal device clock generating means which generates an internaldevice clock synchronized to a time halfway between said early and saidlate bus clock signals.
 109. The semiconductor device of claim 108wherein said bus further includes a first and a second one of said busclock lines, said first bus clock line carries said early bus clocksignal and said second bus clock line carries said late bus clocksignal, said semiconductor device further comprising a means to detectsaid early bus clock signal on said first bus clock line and a means todetect said late bus clock signal on said second bus clock line. 110.The semiconductor device of claim 109 wherein said semiconductor deviceis a memory device which connects substantially only to said bus andsends and receives substantially all address, data and controlinformation over said bus.
 111. A semiconductor device capable of use ina semiconductor bus architecture including a plurality of semiconductordevices connected in parallel to a bus wherein said bus includes aplurality of bus lines for carrying as a sequential series of bitssubstantially all address, data, control and device-select informationneeded by said semiconductor device for communication with substantiallyevery other semiconductor device connected to said bus, and hassubstantially fewer bus lines than the number of bits in a singleaddress, and carries device-select information for said semiconductordevice without the need for a separate device-select line connecteddirectly to said individual semiconductor device, said semiconductordevice comprising connection means adapted to connect said semiconductordevice to said bus, a plurality of input receivers connected to one ofsaid bus data lines and a selection means for selecting said inputreceivers one by one to sense and store, one at a time, the bits of saidsequential series of bits.
 112. The semiconductor device of claim 111wherein said semiconductor device is a memory device which connectssubstantially only to said bus and sends and receives substantially alladdress, data and control information over said bus.
 113. Thesemiconductor device of claim 112 wherein two input receivers areconnected to one of said bus lines.
 114. A semiconductor device capableof use in an architecture for a semiconductor system bus including aplurality of semiconductor devices connected in parallel to a buswherein said bus system includes a plurality of bus lines for carryingsubstantially all address, data, control and device-select informationneeded by said semiconductor device for communication with substantiallyevery other semiconductor device connected to said system bus, and hassubstantially fewer bus lines than the number of bits in a singleaddress, and carries device-select information for said semiconductordevice without the need for a separate device-select line connecteddirectly to said individual semiconductor device, said semiconductordevice comprising connection means adapted to connect said semiconductordevice to said system bus, an internal input/output bus within saidsemiconductor device having more lines than said system bus, and a meansfor multiplexing the lines of said internal bus to the lines of saidsystem bus, whereby said system bus can run at a higher speed than saidinternal bus.
 115. The semiconductor device of claim 114 wherein saidsemiconductor device is a memory device which connects substantiallyonly to said system bus and sends and receives substantially alladdress, data and control information over said system bus.
 116. Asemiconductor device capable of use in an architecture for asemiconductor system bus including a plurality of semiconductor devicesconnected in parallel to a bus wherein said system bus includes aplurality of bus lines for carrying substantially all address, data,control and device-select information needed by said semiconductordevice for communication with substantially every other semiconductordevice connected to said system bus, and has substantially fewer buslines than the number of bits in a single address, and carriesdevice-select information for said semiconductor device without the needfor a separate device-select line connected directly to said individualsemiconductor device, said semiconductor device comprising connectionmeans adapted to connect said semiconductor device to said system bus,an internal input/output bus within said semiconductor device havingmore lines than said system bus, a means for multiplexing the lines ofsaid internal bus to the lines of said system bus, whereby said systembus can run at a higher speed than said internal bus, and at least onemodifiable identification register accessible to said system bus throughsaid connection means, whereby data may be transmitted to said registervia said system bus and which enables said device thereafter to beuniquely identified.
 117. The semiconductor device of claim 116 whereinsaid semiconductor device is a memory device which connectssubstantially only to said system bus and sends and receivessubstantially all address, data and control information over said systembus.
 118. A semiconductor device capable of use in an architecture for asemiconductor system bus including a plurality of semiconductor devicesconnected in parallel to a bus wherein said system bus includes aplurality of bus lines for carrying substantially all address, data,control and device-select information needed by said semiconductordevice for communication with substantially every other semiconductordevice connected to said system bus, and has substantially fewer buslines than the number of bits in a single address, and carriesdevice-select information for said semiconductor device without the needfor a separate device-select line connected directly to said individualsemiconductor device, said semiconductor device comprising connectionmeans adapted to connect said semiconductor device to said system bus,an internal input/output bus within said semiconductor device havingmore lines than said system bus, a means for multiplexing the lines ofsaid internal bus to the lines of said system bus, whereby said systembus can run at a higher speed than said internal bus, and at least onemodifiable register to hold device address information, said modifiableregister accessible to said system bus through said connection means,whereby data may be transmitted to said register via said system buswhich enables said device thereafter to respond to a predetermined rangeof addresses.
 119. The semiconductor device of claim 118 wherein saidsemiconductor device is a memory device which connectssubstantially-only to said system bus and sends and receivessubstantially all address, data and control information over said systembus.
 120. The semiconductor device of claim 119 wherein said memorydevice has at least one discrete memory section and also has at leastone modifiable address register adapted to store memory addressinformation which corresponds to each said discrete memory section. 121.A semiconductor device capable of use in an architecture for asemiconductor system bus including a plurality of semiconductor devicesconnected in parallel to a bus wherein said system bus includes aplurality of bus lines for carrying substantially all address, data andcontrol information needed by said semiconductor device forcommunication with substantially every other semiconductor deviceconnected to said system bus, and has substantially fewer bus lines thanthe number of bits in a single address, said semiconductor devicecomprising connection means adapted to connect said semiconductor deviceto said system bus, an internal input/output bus within saidsemiconductor device having more lines than said system bus, a means formultiplexing the lines of said internal bus to the lines of said systembus, whereby said system bus can run at a higher speed than saidinternal bus, and at least one modifiable access-time registeraccessible to said system bus through said connection means, wherebydata may be transmitted to said register via said system bus whichestablishes a predetermined amount of time that said semiconductordevice thereafter must wait before using said system bus in response toa request.
 122. The semiconductor device of claim 121 wherein saidsemiconductor device is a memory device which connects substantiallyonly to said system bus and sends and receives substantially alladdress, data and control information over said system bus.
 123. Thesemiconductor device of claim 121 further comprising at least twoaccess-time registers and one of said access-time registers ispermanently programmed to contain a fixed value and at least one of saidaccess-time registers can be modified by information carried on saidsystem bus.
 124. A semiconductor device capable of use in asemiconductor bus architecture including a plurality of semiconductordevices connected in parallel to a bus wherein said bus includes aplurality of bus lines for carrying substantially all address, data,control and device-select information needed by said semiconductordevice for communication with substantially every other semiconductordevice connected to said bus, and has substantially fewer bus lines thanthe number of bits in a single address, and carries device-selectinformation for said semiconductor device without the need for aseparate device-select line connected directly to said individualsemiconductor device, wherein said address, data, control anddevice-select information is carried over said bus in the form ofrequest packets and bus transactions, said semiconductor devicecomprising connection means adapted to connect said semiconductor deviceto said bus, a means to receive said request packets over said bus, ameans to decode information in said request packets, and a means torespond to said information in said request packets.
 125. Thesemiconductor device of claim 124 wherein said means to decodeinformation in said request packet further comprises a means to identifyand decode said control information in said request packet, a means toidentify and decode said device-select information in said requestpacket, a means to identify and decode said address information in saidrequest packet and a means to determine whether said control informationor said address information instructs said semiconductor device to begina response.
 126. The semiconductor device of claim 124 wherein each ofsaid bus transactions is carried out in response to said address andsaid control information in one of said request packets, and whereinsaid means to identify and decode information in said request packetsincludes a means to identify a sequence of bytes on said bus as one ofsaid request packets containing said address and said controlinformation, said control information including information about thetype of said bus transaction being requested and the access time whichneeds to intervene before beginning said bus transaction over said busand said address and said control information includes device-selectinformation instructing one or more said semiconductor devices torespond to said address and said control information.
 127. Thesemiconductor device of claim 124 further comprising a plurality ofsense amplifiers adapted to precharge to a selected state or to latch abit of information, a means to hold said sense amplifiers in anunmodified state after latching one of said bits of information, a meansto precharge said sense amplifiers and a means for selecting whethersaid semiconductor device should precharge said sense amplifiers orshould hold said sense amplifiers in an unmodified state.
 128. Thesemiconductor device of claim 124 wherein said means to respond to saidinformation, where said information is control information, furthercomprises a means to transfer a data block during a data block transfer,further including a means to read data from said semiconductor deviceand write data into said semiconductor device, and initiate a data blocktransfer, transfer a data block of a selected size, transfer a datablock at a selected time, access a control register, including a meansto read from or write to said control register, or select normal orpage-mode access.
 129. The semiconductor device of claim 124 furthercomprising a means to respond to said information in said request packetif said information includes a device identification number unique tosaid semiconductor device.
 130. The semiconductor device of claim 124further comprising a means to respond to said information in saidrequest packet if said information includes a special deviceidentification number which calls for said semiconductor device torespond.
 131. The semiconductor device of claim 124 further comprising ameans to respond to said information in said request packet if saidinformation includes an address unique to said semiconductor device.132. The semiconductor device of claim 124 further comprising a means tointerpret said control information and decode the time to wait beforebeginning said bus transaction over said bus.
 133. The semiconductordevice of claim 124 further comprising a means to interpret said controlinformation and decode the size of a data block to transfer during oneof said bus transactions.
 134. The semiconductor device of claim 124,125, 126, 127, 128, 129, 130, 131, 132 or 133 wherein said semiconductordevice is a memory device which connects substantially only to said busand sends and receives substantially all address, data and controlinformation over said bus.
 135. A semiconductor device capable of use ina semiconductor bus architecture including a plurality of semiconductordevices connected in parallel to a bus wherein said bus includes aplurality of bus lines for carrying substantially all address, data,control and device-select information needed by said semiconductordevice for communication with substantially every other semiconductordevice connected to said bus, and has substantially fewer bus lines thanthe number of bits in a single address, and carries device-selectinformation for said semiconductor device without the need for aseparate device-select line connected directly to said individualsemiconductor device, wherein said address, data, control anddevice-select information is carried over said bus in the form ofrequest packets and bus transactions, said semiconductor devicecomprising connection means adapted to connect said semiconductor deviceto said bus, a means to encode address and control information in saidrequest packets and a means to send said request packets over said bus.136. The semiconductor device of claim 135 further comprising a means torequest a bus transaction wherein each of said bus transactions iscarried out in response to said address and said control information inone of said request packets, and wherein said means to encodeinformation in said request packets includes a means to mark a sequenceof bytes on said bus as one of said request packets, said controlinformation including information about the type of said bus transactionbeing requested and the access time which needs to intervene beforebeginning said bus transaction over said bus and said address and saidcontrol information includes device-select information instructing oneor more said semiconductor devices to respond to said address and saidcontrol information.
 137. The semiconductor device of claim 135 whereinone or more of said plurality of semiconductor devices has a uniquedevice identification number, said semiconductor device furthercomprising a means to send control information to a specific one of saidplurality of semiconductor devices by including in said request packet aselected said device identification number.
 138. The semiconductordevice of claim 135 wherein each of said plurality of semiconductordevices is adapted to respond to a special device identification number,said semiconductor device further comprising a means to send controlinformation to each of said plurality of semiconductor devices byincluding in said request packet said special device identificationnumber.
 139. The semiconductor device of claim 135 wherein one or moreof said plurality of semiconductor devices is a memory device having aplurality of addresses, said semiconductor device further comprising ameans to send control information to a specific address or range ofaddresses in one of said plurality of semiconductor devices by includingsaid specific address or range of addresses in said request packet. 140.The semiconductor device of claim 135 wherein at least one of saidrequest packets is a request packet requesting a bus transaction whichis followed by a corresponding one of said bus transactions, saidsemiconductor device further comprising a means to encode said controlinformation to specify directly or indirectly the time between the endof said request packet requesting a bus transaction and saidcorresponding bus transaction over said bus.
 141. The semiconductordevice of claim 140 wherein one type of said bus transactions is atransfer of a data block, said semiconductor device further comprising ameans to encode said control information to specify the size of saiddata block to transfer.
 142. The semiconductor device of claim 140further comprising a means to keep track of current and pending bustransactions, whereby collisions on said bus are avoided because saidsemiconductor device avoids initiating bus transactions which wouldconflict with current or pending bus transactions.
 143. Thesemiconductor device of claim 135 wherein said semiconductor device is afirst master device and one of said plurality of semiconductor devicesis a second master device, further comprising a collision detectingmeans whereby said first master device when sending a first one of saidrequest packets can detect said second master device sending a collidingone of said request packets, where said colliding request packet may besent simultaneous with the initial sending of or overlapping the sendingof said first request packet, and an arbitration means whereby saidfirst and said second master devices select a priority order in whicheach of said master devices will be allowed to access said bussequentially.
 144. The semiconductor device of claim 143 wherein saidsemiconductor device is a master device and at least one of saidplurality of semiconductor devices is a master device, each of saidmaster devices has a master ID number and each of said request packetsincludes a master ID position which is a predetermined number of bits ina predetermined position in said request packet, and wherein saidcollision detection means comprises a means for said semiconductordevice to send its master ID number in said request packet and a meansto detect a collision and invoke said arbitration means if saidsemiconductor device detects any other master ID number in said masterID position.
 145. The semiconductor device of claim 144 wherein saidsystem bus architecture includes a means for carrying information onsaid bus during bus cycles, said semiconductor device further comprisinga means for driving a selected bus line or lines during at least oneselected bus cycle while sending each said request packet, a means formonitoring said selected bus line or lines to see if another said masterdevice is sending one of said colliding request packets and a means forinforming all said master devices that a collision has occurred and forinvoking said arbitration means.
 146. The semiconductor device of claim145 further comprising a means, when sending a request packet, fordriving a selected bus line or lines with a certain current during atleast one selected bus cycle, a means for monitoring said selected busline or lines for a greater than normal current to see if another saidmaster device is driving that line or lines, a means for detecting saidgreater than normal current, and a means for informing all said masterdevices that a collision has occurred and for invoking said arbitrationmeans.
 147. The semiconductor device of claim 143 wherein saidarbitration means comprises a means for initiating an arbitration cycle,a means for allocating a single bus line to each said master deviceduring at least one selected bus cycle relative to the start of saidarbitration cycle, a means for allocating each said master device to asingle bus line during one of said selected bus cycles if there are moremaster devices than available bus lines, a means for each of said masterdevices which sent one of said colliding request packets to drive saidbus line allocated to said master device during said selected bus cycle,and a means in at least one of said master devices for storinginformation about which master devices sent one of said collidingrequest packets, whereby said master devices can monitor selected buslines during said arbitration cycle and identify each said master devicewhich sent one of said colliding request packets.
 148. The semiconductordevice of claim 143 wherein said arbitration means comprises a means foridentifying each of said master devices which sent one of said collidingrequest packets, a means for assigning a priority to each said masterdevice which sent one of said colliding request packets, and a means forallowing each said master device which sent one of said collidingrequest packets to access the bus sequentially according to thatpriority.
 149. The semiconductor device of claim 143 wherein saidpriority is based on the physical location of each of said masterdevices.
 150. The semiconductor device of claim 143 wherein saidpriority is based on said master ID number of said master devices.